@@ -91,6 +91,9 @@
@X_tp_a_bp_rc ...... ....0 ra:5 ....0 .......... rc:1 &X_rc rt=%x_frtp rb=%x_frbp
+&X_t rt
+@X_t ...... rt:5 ..... ..... .......... . &X_t
+
&X_t_rc rt rc:bool
@X_t_rc ...... rt:5 ..... ..... .......... rc:1 &X_t_rc
@@ -318,6 +321,7 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
### Move To/From FPSCR
MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc
+MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t
### Decimal Floating-Point Arithmetic Instructions
@@ -607,7 +607,7 @@ static void gen_mffs(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
-static void do_mffsc(int rt)
+static void do_mffsc(int rt, uint64_t set_mask)
{
TCGv_i64 fpscr;
@@ -615,6 +615,7 @@ static void do_mffsc(int rt)
gen_reset_fpstatus();
tcg_gen_extu_tl_i64(fpscr, cpu_fpscr);
+ tcg_gen_andi_i64(fpscr, fpscr, set_mask);
set_fpr(rt, fpscr);
tcg_temp_free_i64(fpscr);
@@ -624,7 +625,7 @@ static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a)
{
REQUIRE_FPU(ctx);
- do_mffsc(a->rt);
+ do_mffsc(a->rt, 0xFFFFFFFFFFFFFFFFULL);
if (a->rc) {
gen_set_cr1_from_fpscr(ctx);
}
@@ -632,26 +633,14 @@ static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a)
return true;
}
-/* mffsl */
-static void gen_mffsl(DisasContext *ctx)
+static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a)
{
- TCGv_i64 t0;
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_FPU(ctx);
- if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
- return gen_mffs(ctx);
- }
+ do_mffsc(a->rt, FP_DRN | FP_STATUS | FP_ENABLES | FP_NI | FP_RN);
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- tcg_gen_extu_tl_i64(t0, cpu_fpscr);
- /* Mask everything except mode, status, and enables. */
- tcg_gen_andi_i64(t0, t0, FP_DRN | FP_STATUS | FP_ENABLES | FP_RN);
- set_fpr(rD(ctx->opcode), t0);
- tcg_temp_free_i64(t0);
+ return true;
}
/* mffsce */
@@ -77,8 +77,6 @@ GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT,
PPC2_ISA300),
-GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
- PPC2_ISA300),
GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x00000000, PPC_FLOAT,
PPC_NONE),
GEN_HANDLER_E_2(mffscrni, 0x3F, 0x07, 0x12, 0x17, 0x00000000, PPC_FLOAT,
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> --- target/ppc/insn32.decode | 4 ++++ target/ppc/translate/fp-impl.c.inc | 27 ++++++++------------------- target/ppc/translate/fp-ops.c.inc | 2 -- 3 files changed, 12 insertions(+), 21 deletions(-)