@@ -130,6 +130,9 @@
&X_imm2 rt imm
@X_imm2 ...... rt:5 ..... ... imm:2 .......... . &X_imm2
+&X_imm3 rt imm
+@X_imm3 ...... rt:5 ..... .. imm:3 .......... . &X_imm3
+
%x_xt 0:1 21:5
&X_imm5 xt imm:uint8_t vrb
@X_imm5 ...... ..... imm:5 vrb:5 .......... . &X_imm5 xt=%x_xt
@@ -330,7 +333,9 @@ MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc
MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t
MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t
MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
+MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb
MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
+MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3
### Decimal Floating-Point Arithmetic Instructions
@@ -679,6 +679,41 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a)
return true;
}
+static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb *a)
+{
+ TCGv_i64 t1;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_FPU(ctx);
+
+ t1 = tcg_temp_new_i64();
+ get_fpr(t1, a->rb);
+ tcg_gen_andi_i64(t1, t1, FP_DRN);
+
+ do_mffsc(a->rt, t1, FP_DRN | FP_ENABLES | FP_NI | FP_RN, ~FP_DRN, 0x0100);
+
+ tcg_temp_free_i64(t1);
+
+ return true;
+}
+
+static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a)
+{
+ TCGv_i64 t1;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_FPU(ctx);
+
+ t1 = tcg_temp_new_i64();
+ tcg_gen_movi_i64(t1, (uint64_t)a->imm << FPSCR_DRN0);
+
+ do_mffsc(a->rt, t1, FP_DRN | FP_ENABLES | FP_NI | FP_RN, ~FP_DRN, 0x0100);
+
+ tcg_temp_free_i64(t1);
+
+ return true;
+}
+
/* mtfsb0 */
static void gen_mtfsb0(DisasContext *ctx)
{
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> --- target/ppc/insn32.decode | 5 +++++ target/ppc/translate/fp-impl.c.inc | 35 ++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+)