@@ -353,6 +353,7 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+#define M_MSR_GS (1ull << MSR_GS)
#define M_MSR_POW (1ull << MSR_POW)
#define M_MSR_CE (1ull << MSR_CE)
#define M_MSR_ILE (1ull << MSR_ILE)
@@ -478,7 +479,6 @@ typedef enum {
#define msr_hv (0)
#endif
#define msr_cm ((env->msr >> MSR_CM) & 1)
-#define msr_gs ((env->msr >> MSR_GS) & 1)
#define msr_fp ((env->msr >> MSR_FP) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
@@ -233,7 +233,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
}
if ((env->mmu_model == POWERPC_MMU_BOOKE ||
env->mmu_model == POWERPC_MMU_BOOKE206) &&
- ((value >> MSR_GS) & 1) != msr_gs) {
+ !(value & env->msr & M_MSR_GS)) {
cpu_interrupt_exittb(cs);
}
if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
@@ -935,7 +935,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
}
if (((env->spr[SPR_BOOKE_MAS0] & MAS0_ATSEL) == MAS0_ATSEL_LRAT) &&
- !msr_gs) {
+ !(env->msr & M_MSR_GS)) {
/* XXX we don't support direct LRAT setting yet */
fprintf(stderr, "cpu: don't support LRAT setting yet\n");
return;
@@ -962,7 +962,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
POWERPC_EXCP_INVAL_INVAL, GETPC());
}
- if (msr_gs) {
+ if (env->msr & M_MSR_GS) {
cpu_abort(env_cpu(env), "missing HV implementation\n");
}
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> --- target/ppc/cpu.h | 2 +- target/ppc/helper_regs.c | 2 +- target/ppc/mmu_helper.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-)