diff mbox series

[15/20] target/ppc: Substitute msr_dr macro with new M_MSR_DR macro

Message ID 20220422185450.107256-16-victor.colombo@eldorado.org.br (mailing list archive)
State New, archived
Headers show
Series target/ppc: Remove hidden usages of *env | expand

Commit Message

Víctor Colombo April 22, 2022, 6:54 p.m. UTC 
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
 target/ppc/cpu.h         | 2 +-
 target/ppc/helper_regs.c | 2 +-
 target/ppc/mmu_common.c  | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cc0b5d72de..3a5218a2cd 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -363,6 +363,7 @@  typedef enum {
 #define M_MSR_FP (1ull << MSR_FP)
 #define M_MSR_ME (1ull << MSR_ME)
 #define M_MSR_IR (1ull << MSR_IR)
+#define M_MSR_DR (1ull << MSR_DR)
 #define M_MSR_DS (1ull << MSR_DS)
 #define M_MSR_LE (1ull << MSR_LE)
 
@@ -484,7 +485,6 @@  typedef enum {
 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
-#define msr_dr   ((env->msr >> MSR_DR)   & 1)
 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 
 #define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index fa8f213cd5..1c67fbf7c1 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -228,7 +228,7 @@  int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
         value |= env->msr & MSR_HVB;
     }
     if (!(value & env->msr & M_MSR_IR) ||
-        ((value >> MSR_DR) & 1) != msr_dr) {
+        !(value & env->msr & M_MSR_DR)) {
         cpu_interrupt_exittb(cs);
     }
     if ((env->mmu_model == POWERPC_MMU_BOOKE ||
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 918c15f78d..dbb657d9bc 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -388,7 +388,7 @@  static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
                   " nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx
                   " ir=%d dr=%d pr=%d %d t=%d\n",
                   eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr,
-                  !!(env->msr & M_MSR_IR), (int)msr_dr, pr ? 1 : 0,
+                  !!(env->msr & M_MSR_IR), !!(env->msr & M_MSR_DR), pr ? 1 : 0,
                   access_type == MMU_DATA_STORE, type);
     pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
     hash = vsid ^ pgidx;
@@ -627,7 +627,7 @@  found_tlb:
 
     /* Check the address space */
     if ((access_type == MMU_INST_FETCH ?
-        !!(env->msr & M_MSR_IR) : msr_dr) != (tlb->attr & 1)) {
+        !!(env->msr & M_MSR_IR) : !!(env->msr & M_MSR_DR)) != (tlb->attr & 1)) {
         qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
         return -1;
     }
@@ -1171,7 +1171,7 @@  int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
 {
     int ret = -1;
     bool real_mode = (type == ACCESS_CODE && !(env->msr & M_MSR_IR))
-        || (type != ACCESS_CODE && msr_dr == 0);
+        || (type != ACCESS_CODE && !(env->msr & M_MSR_DR));
 
     switch (env->mmu_model) {
     case POWERPC_MMU_SOFT_6xx: