@@ -362,6 +362,7 @@ typedef enum {
#define M_MSR_PR (1ull << MSR_PR)
#define M_MSR_FP (1ull << MSR_FP)
#define M_MSR_ME (1ull << MSR_ME)
+#define M_MSR_EP (1ull << MSR_EP)
#define M_MSR_IR (1ull << MSR_IR)
#define M_MSR_DR (1ull << MSR_DR)
#define M_MSR_DS (1ull << MSR_DS)
@@ -484,7 +485,6 @@ typedef enum {
#endif
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
-#define msr_ep ((env->msr >> MSR_EP) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)
@@ -241,8 +241,8 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
/* Swap temporary saved registers with GPRs */
hreg_swap_gpr_tgpr(env);
}
- if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
- env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
+ if (unlikely(!(value & env->msr & M_MSR_EP))) {
+ env->excp_prefix = !!(value & M_MSR_EP) * 0xFFF00000;
}
/*
* If PR=1 then EE, IR and DR must be 1
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> --- target/ppc/cpu.h | 2 +- target/ppc/helper_regs.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)