diff mbox series

[20/20] target/ppc: Add unused M_MSR_* macros

Message ID 20220422185450.107256-21-victor.colombo@eldorado.org.br (mailing list archive)
State New, archived
Headers show
Series target/ppc: Remove hidden usages of *env | expand

Commit Message

Víctor Colombo April 22, 2022, 6:54 p.m. UTC 
Add M_MSR_* macros for msr bits that had an unused msr_* before.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
 target/ppc/cpu.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
diff mbox series

Patch

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 3cbecc96d8..dda289a121 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -353,6 +353,9 @@  typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 
+#define M_MSR_SF (1ull << MSR_SF)
+#define M_MSR_TAG (1ull << MSR_TAG)
+#define M_MSR_ISF (1ull << MSR_ISF)
 #if defined(TARGET_PPC64)
 #define M_MSR_HV (1ull << MSR_HV)
 #else
@@ -360,10 +363,20 @@  typedef enum {
 #endif
 #define M_MSR_TS0 (1ull << MSR_TS0)
 #define M_MSR_TS1 (1ull << MSR_TS1)
+#define M_MSR_TM (1ull << MSR_TM)
 #define M_MSR_TS (M_MSR_TS0 | M_MSR_TS1)
 #define M_MSR_CM (1ull << MSR_CM)
+#define M_MSR_ICM (1ull << MSR_ICM)
 #define M_MSR_GS (1ull << MSR_GS)
+#define M_MSR_UCLE (1ull << MSR_UCLE)
+#define M_MSR_VR (1ull << MSR_VR)
+#define M_MSR_SPE (1ull << MSR_SPE)
+#define M_MSR_VSX (1ull << MSR_VSX)
+#define M_MSR_S (1ull << MSR_S)
+#define M_MSR_KEY (1ull << MSR_KEY)
 #define M_MSR_POW (1ull << MSR_POW)
+#define M_MSR_WE (1ull << MSR_WE)
+#define M_MSR_TGPR (1ull << MSR_TGPR)
 #define M_MSR_CE (1ull << MSR_CE)
 #define M_MSR_ILE (1ull << MSR_ILE)
 #define M_MSR_EE (1ull << MSR_EE)
@@ -373,10 +386,21 @@  typedef enum {
 #define M_MSR_FE0 (1ull << MSR_FE0)
 #define M_MSR_FE1 (1ull << MSR_FE1)
 #define M_MSR_FE (M_MSR_FE0 | M_MSR_FE1)
+#define M_MSR_SE (1ull << MSR_SE)
+#define M_MSR_DWE (1ull << MSR_DWE)
+#define M_MSR_UBLE (1ull << MSR_UBLE)
+#define M_MSR_BE (1ull << MSR_BE)
+#define M_MSR_DE (1ull << MSR_DE)
+#define M_MSR_AL (1ull << MSR_AL)
 #define M_MSR_EP (1ull << MSR_EP)
 #define M_MSR_IR (1ull << MSR_IR)
 #define M_MSR_DR (1ull << MSR_DR)
+#define M_MSR_IS (1ull << MSR_IS)
 #define M_MSR_DS (1ull << MSR_DS)
+#define M_MSR_PE (1ull << MSR_PE)
+#define M_MSR_PX (1ull << MSR_PX)
+#define M_MSR_PMM (1ull << MSR_PMM)
+#define M_MSR_RI (1ull << MSR_RI)
 #define M_MSR_LE (1ull << MSR_LE)
 
 /* PMU bits */