[v2,20/21] target/ppc: Add unused msr bits FIELDs

Commit Message

Víctor Colombo May 2, 2022, 2:39 p.m. UTC

Add FIELDs macros for msr bits that had an unused msr_* before.

Signed-off-by: Víctor Colombo <[e-mail]>

---

v2: Remove M_MSR_* and use FIELD macro now.
Signed-off-by: Víctor Colombo <[e-mail]>
---
 target/ppc/cpu.h | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Richard Henderson May 2, 2022, 10:01 p.m. UTC | #1

On 5/2/22 07:39, Víctor Colombo wrote:
> Add FIELDs macros for msr bits that had an unused msr_* before.
> 
> Signed-off-by: Víctor Colombo<[e-mail]>

Acked-by: Richard Henderson <[e-mail]>

r~

Patch

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 9b765af4db..5cd9d88555 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,16 +354,31 @@  typedef enum {
 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 
+FIELD(MSR, SF, MSR_SF, 1)
+FIELD(MSR, TAG, MSR_TAG, 1)
+FIELD(MSR, ISF, MSR_ISF, 1)
 #if defined(TARGET_PPC64)
 FIELD(MSR, HV, MSR_HV, 1)
 #define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
 #else
 #define FIELD_EX64_HV(storage) 0
 #endif
+FIELD(MSR, TS0, MSR_TS0, 1)
+FIELD(MSR, TS1, MSR_TS1, 1)
 FIELD(MSR, TS, MSR_TS0, 2)
+FIELD(MSR, TM, MSR_TM, 1)
 FIELD(MSR, CM, MSR_CM, 1)
+FIELD(MSR, ICM, MSR_ICM, 1)
 FIELD(MSR, GS, MSR_GS, 1)
+FIELD(MSR, UCLE, MSR_UCLE, 1)
+FIELD(MSR, VR, MSR_VR, 1)
+FIELD(MSR, SPE, MSR_SPE, 1)
+FIELD(MSR, VSX, MSR_VSX, 1)
+FIELD(MSR, S, MSR_S, 1)
+FIELD(MSR, KEY, MSR_KEY, 1)
 FIELD(MSR, POW, MSR_POW, 1)
+FIELD(MSR, WE, MSR_WE, 1)
+FIELD(MSR, TGPR, MSR_TGPR, 1)
 FIELD(MSR, CE, MSR_CE, 1)
 FIELD(MSR, ILE, MSR_ILE, 1)
 FIELD(MSR, EE, MSR_EE, 1)
@@ -373,10 +388,21 @@  FIELD(MSR, ME, MSR_ME, 1)
 /* MSR_FE0 and MSR_FE1 are not side-by-side so we can't combine them */
 FIELD(MSR, FE0, MSR_FE0, 1)
 FIELD(MSR, FE1, MSR_FE1, 1)
+FIELD(MSR, SE, MSR_SE, 1)
+FIELD(MSR, DWE, MSR_DWE, 1)
+FIELD(MSR, UBLE, MSR_UBLE, 1)
+FIELD(MSR, BE, MSR_BE, 1)
+FIELD(MSR, DE, MSR_DE, 1)
+FIELD(MSR, AL, MSR_AL, 1)
 FIELD(MSR, EP, MSR_EP, 1)
 FIELD(MSR, IR, MSR_IR, 1)
 FIELD(MSR, DR, MSR_DR, 1)
+FIELD(MSR, IS, MSR_IS, 1)
 FIELD(MSR, DS, MSR_DS, 1)
+FIELD(MSR, PE, MSR_PE, 1)
+FIELD(MSR, PX, MSR_PX, 1)
+FIELD(MSR, PMM, MSR_PMM, 1)
+FIELD(MSR, RI, MSR_RI, 1)
 FIELD(MSR, LE, MSR_LE, 1)
 
 /* PMU bits */