From patchwork Tue May 3 20:24:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?V=C3=ADctor_Colombo?= X-Patchwork-Id: 12836464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64370C433F5 for ; Tue, 3 May 2022 22:36:27 +0000 (UTC) Received: from localhost ([::1]:41876 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nm185-0007k2-U5 for qemu-devel@archiver.kernel.org; Tue, 03 May 2022 18:36:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nlz7Y-0006tY-Go; Tue, 03 May 2022 16:27:46 -0400 Received: from [187.72.171.209] (port=8548 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nlz7X-0005tQ-0w; Tue, 03 May 2022 16:27:44 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Tue, 3 May 2022 17:25:38 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 65A0B800491; Tue, 3 May 2022 17:25:38 -0300 (-03) From: =?utf-8?q?V=C3=ADctor_Colombo?= To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, balaton@eik.bme.hu, victor.colombo@eldorado.org.br Subject: [PATCH v3 13/21] target/ppc: Remove msr_cm macro Date: Tue, 3 May 2022 17:24:33 -0300 Message-Id: <20220503202441.129549-14-victor.colombo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220503202441.129549-1-victor.colombo@eldorado.org.br> References: <20220503202441.129549-1-victor.colombo@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 03 May 2022 20:25:38.0837 (UTC) FILETIME=[F3F1C450:01D85F2B] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass client-ip=187.72.171.209; envelope-from=victor.colombo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" msr_cm macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter. Suggested-by: Richard Henderson Signed-off-by: Víctor Colombo Reviewed-by: Richard Henderson --- v3: fix this patch's name (msr_ce --> msr_cm) Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 2 +- target/ppc/mmu_common.c | 2 +- target/ppc/mmu_helper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 294c61c9dc..8e652691cf 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -354,6 +354,7 @@ typedef enum { #define MSR_RI 1 /* Recoverable interrupt 1 */ #define MSR_LE 0 /* Little-endian mode 1 hflags */ +FIELD(MSR, CM, MSR_CM, 1) FIELD(MSR, GS, MSR_GS, 1) FIELD(MSR, POW, MSR_POW, 1) FIELD(MSR, CE, MSR_CE, 1) @@ -480,7 +481,6 @@ FIELD(MSR, LE, MSR_LE, 1) #else #define msr_hv (0) #endif -#define msr_cm ((env->msr >> MSR_CM) & 1) #define msr_fe0 ((env->msr >> MSR_FE0) & 1) #define msr_fe1 ((env->msr >> MSR_FE1) & 1) #define msr_ep ((env->msr >> MSR_EP) & 1) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 7e77b9b84a..031bb4493b 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -692,7 +692,7 @@ int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr mask; uint32_t tlb_pid; - if (!msr_cm) { + if (!FIELD_EX64(env->msr, MSR, CM)) { /* In 32bit mode we can only address 32bit EAs */ address = (uint32_t)address; } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 5bb5c71038..15239dc95b 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1003,7 +1003,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) /* Add a mask for page attributes */ mask |= MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MAS2_E; - if (!msr_cm) { + if (!FIELD_EX64(env->msr, MSR, CM)) { /* * Executing a tlbwe instruction in 32-bit mode will set bits * 0:31 of the TLB EPN field to zero.