@@ -354,6 +354,7 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+FIELD(MSR, CM, MSR_CM, 1)
FIELD(MSR, GS, MSR_GS, 1)
FIELD(MSR, POW, MSR_POW, 1)
FIELD(MSR, CE, MSR_CE, 1)
@@ -480,7 +481,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#else
#define msr_hv (0)
#endif
-#define msr_cm ((env->msr >> MSR_CM) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
#define msr_de ((env->msr >> MSR_DE) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
@@ -692,7 +692,7 @@ int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
hwaddr mask;
uint32_t tlb_pid;
- if (!msr_cm) {
+ if (!FIELD_EX64(env->msr, MSR, CM)) {
/* In 32bit mode we can only address 32bit EAs */
address = (uint32_t)address;
}
@@ -1003,7 +1003,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
/* Add a mask for page attributes */
mask |= MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MAS2_E;
- if (!msr_cm) {
+ if (!FIELD_EX64(env->msr, MSR, CM)) {
/*
* Executing a tlbwe instruction in 32-bit mode will set bits
* 0:31 of the TLB EPN field to zero.