diff mbox series

[2/2] target/riscv: disable zb* extensions by default

Message ID 20220516033357.12371-2-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series [1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize | expand

Commit Message

Weiwei Li May 16, 2022, 3:33 a.m. UTC 
- enable zb* extensions by default will make cpu types(such as sifive-u34) implicitly support zb* extensions

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Alistair Francis May 17, 2022, 12:33 a.m. UTC | #1 
On Mon, May 16, 2022 at 1:34 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
>  - enable zb* extensions by default will make cpu types(such as sifive-u34) implicitly support zb* extensions

Agh, this is a pain.

Can you enable these by default for the base machines then? That way
they will be enabled for the virt machine

Alistair

>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>  target/riscv/cpu.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b12f69c584..a3a17323e7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -847,13 +847,13 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
>      DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>
> -    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> -    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> -    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> +    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, false),
> +    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, false),
> +    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, false),
>      DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
>      DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
>      DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
> -    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> +    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, false),
>      DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
>      DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
>      DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
> --
> 2.17.1
>
>
Alistair Francis May 17, 2022, 12:54 a.m. UTC | #2 
On Tue, May 17, 2022 at 10:33 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Mon, May 16, 2022 at 1:34 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
> >
> >  - enable zb* extensions by default will make cpu types(such as sifive-u34) implicitly support zb* extensions
>
> Agh, this is a pain.
>
> Can you enable these by default for the base machines then? That way
> they will be enabled for the virt machine

Actually, come to think of it, we can probably just register the
riscv_cpu_properties for the base cpus. That way only those CPUs can
be configured by the user. Can you do that instead?

Alistair

>
> Alistair
>
> >
> > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> > ---
> >  target/riscv/cpu.c | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index b12f69c584..a3a17323e7 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -847,13 +847,13 @@ static Property riscv_cpu_properties[] = {
> >      DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> >      DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> >
> > -    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> > -    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> > -    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> > +    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, false),
> > +    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, false),
> > +    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, false),
> >      DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
> >      DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
> >      DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
> > -    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> > +    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, false),
> >      DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
> >      DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
> >      DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
> > --
> > 2.17.1
> >
> >
Weiwei Li May 17, 2022, 1:34 a.m. UTC | #3 
在 2022/5/17 上午8:54, Alistair Francis 写道:
> On Tue, May 17, 2022 at 10:33 AM Alistair Francis <alistair23@gmail.com> wrote:
>> On Mon, May 16, 2022 at 1:34 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>>>   - enable zb* extensions by default will make cpu types(such as sifive-u34) implicitly support zb* extensions
>> Agh, this is a pain.
>>
>> Can you enable these by default for the base machines then? That way
>> they will be enabled for the virt machine
> Actually, come to think of it, we can probably just register the
> riscv_cpu_properties for the base cpus. That way only those CPUs can
> be configured by the user. Can you do that instead?
>
> Alistair
>
Yeah, This is OK. I'll do this later.

Regards,

Weiwei Li

>> Alistair
>>
>>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>>> ---
>>>   target/riscv/cpu.c | 8 ++++----
>>>   1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>>> index b12f69c584..a3a17323e7 100644
>>> --- a/target/riscv/cpu.c
>>> +++ b/target/riscv/cpu.c
>>> @@ -847,13 +847,13 @@ static Property riscv_cpu_properties[] = {
>>>       DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
>>>       DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>>>
>>> -    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
>>> -    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>>> -    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
>>> +    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, false),
>>> +    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, false),
>>> +    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, false),
>>>       DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
>>>       DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
>>>       DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
>>> -    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
>>> +    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, false),
>>>       DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
>>>       DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
>>>       DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
>>> --
>>> 2.17.1
>>>
>>>
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b12f69c584..a3a17323e7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -847,13 +847,13 @@  static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
     DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
 
-    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
-    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
-    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+    DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, false),
+    DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, false),
+    DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, false),
     DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
     DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
     DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
-    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+    DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, false),
     DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
     DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
     DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),