| Message ID | 20220517072645.24938-1-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize | expand |
On Tue, May 17, 2022 at 5:28 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > - setting ext_g will implicitly set ext_i > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/cpu.c | 26 +++++++++++++------------- > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6d01569cad..1c76debb2b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -583,19 +583,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (env->misa_ext == 0) { > uint32_t ext = 0; > > - /* Do some ISA extension error checking */ Can we leave this comment here? Otherwise: Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { > - error_setg(errp, > - "I and E extensions are incompatible"); > - return; > - } > - > - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { > - error_setg(errp, > - "Either I or E extension must be set"); > - return; > - } > - > if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && > cpu->cfg.ext_a && cpu->cfg.ext_f && > cpu->cfg.ext_d && > @@ -610,6 +597,19 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > cpu->cfg.ext_ifencei = true; > } > > + /* Do some ISA extension error checking */ > + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { > + error_setg(errp, > + "I and E extensions are incompatible"); > + return; > + } > + > + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { > + error_setg(errp, > + "Either I or E extension must be set"); > + return; > + } > + > if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { > error_setg(errp, "F extension requires Zicsr"); > return; > -- > 2.17.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6d01569cad..1c76debb2b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -583,19 +583,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (env->misa_ext == 0) { uint32_t ext = 0; - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && cpu->cfg.ext_a && cpu->cfg.ext_f && cpu->cfg.ext_d && @@ -610,6 +597,19 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) cpu->cfg.ext_ifencei = true; } + /* Do some ISA extension error checking */ + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return;