diff mbox series

[RESEND,08/10] target/ppc: implement addg6s

Message ID 20220517164744.58131-9-victor.colombo@eldorado.org.br (mailing list archive)
State New, archived
Headers show
Series BCDA and mffscdrn implementations | expand

Commit Message

Víctor Colombo May 17, 2022, 4:47 p.m. UTC 
From: Matheus Ferst <matheus.ferst@eldorado.org.br>

Implements the following Power ISA v2.06 instruction:
addg6s: Add and Generate Sixes

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
 target/ppc/insn32.decode                   |  4 +++
 target/ppc/translate/fixedpoint-impl.c.inc | 35 ++++++++++++++++++++++
 2 files changed, 39 insertions(+)

Comments

Richard Henderson May 17, 2022, 7:05 p.m. UTC | #1 
On 5/17/22 09:47, Víctor Colombo wrote:
> +static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
> +{
> +    const uint64_t nibbles = 0x0f0f0f0f0f0f0f0fULL,
> +                   carry_bits = 0x1010101010101010ULL;
> +    TCGv t0, t1, t2;
> +
> +    REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
> +
> +    t0 = tcg_temp_new();
> +    t1 = tcg_temp_new();
> +    t2 = tcg_temp_new();
> +
> +    tcg_gen_andi_tl(t0, cpu_gpr[a->ra], nibbles);
> +    tcg_gen_andi_tl(t1, cpu_gpr[a->rb], nibbles);
> +    tcg_gen_add_tl(t0, t0, t1);
> +    tcg_gen_andi_tl(t0, t0, carry_bits);
> +    tcg_gen_shri_tl(t0, t0, 4);
> +
> +    tcg_gen_shri_tl(t1, cpu_gpr[a->ra], 4);
> +    tcg_gen_shri_tl(t2, cpu_gpr[a->rb], 4);
> +    tcg_gen_andi_tl(t1, t1, nibbles);
> +    tcg_gen_andi_tl(t2, t2, nibbles);
> +    tcg_gen_add_tl(t1, t1, t2);
> +    tcg_gen_andi_tl(t1, t1, carry_bits);
> +
> +    tcg_gen_or_tl(t0, t0, t1);
> +    tcg_gen_muli_tl(cpu_gpr[a->rt], t0, 6);

You're supposed to produce a 6 when the carry bit is *not* set.
You need to invert the result of the add before masking w/ carry_bits.

Perhaps

     tcg_gen_add_tl(t0, t0, t1);
     tcg_gen_andc_tl(t0, carry_bits, t0);

r~
diff mbox series

Patch

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a3e87a0867..9d87dd35c0 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -296,6 +296,10 @@  CNTTZDM         011111 ..... ..... ..... 1000111011 -   @X
 PDEPD           011111 ..... ..... ..... 0010011100 -   @X
 PEXTD           011111 ..... ..... ..... 0010111100 -   @X
 
+## BCD Assist
+
+ADDG6S          011111 ..... ..... ..... - 001001010 -  @X
+
 ### Float-Point Load Instructions
 
 LFS             110000 ..... ..... ................     @D
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 1aab32be03..62f5027b5b 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -492,3 +492,38 @@  static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
 #endif
     return true;
 }
+
+static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
+{
+    const uint64_t nibbles = 0x0f0f0f0f0f0f0f0fULL,
+                   carry_bits = 0x1010101010101010ULL;
+    TCGv t0, t1, t2;
+
+    REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
+
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+    t2 = tcg_temp_new();
+
+    tcg_gen_andi_tl(t0, cpu_gpr[a->ra], nibbles);
+    tcg_gen_andi_tl(t1, cpu_gpr[a->rb], nibbles);
+    tcg_gen_add_tl(t0, t0, t1);
+    tcg_gen_andi_tl(t0, t0, carry_bits);
+    tcg_gen_shri_tl(t0, t0, 4);
+
+    tcg_gen_shri_tl(t1, cpu_gpr[a->ra], 4);
+    tcg_gen_shri_tl(t2, cpu_gpr[a->rb], 4);
+    tcg_gen_andi_tl(t1, t1, nibbles);
+    tcg_gen_andi_tl(t2, t2, nibbles);
+    tcg_gen_add_tl(t1, t1, t2);
+    tcg_gen_andi_tl(t1, t1, carry_bits);
+
+    tcg_gen_or_tl(t0, t0, t1);
+    tcg_gen_muli_tl(cpu_gpr[a->rt], t0, 6);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(t2);
+
+    return true;
+}