From patchwork Tue May 24 08:17:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaojuan Yang X-Patchwork-Id: 12859876 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4325C433EF for ; Tue, 24 May 2022 09:11:19 +0000 (UTC) Received: from localhost ([::1]:44240 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ntQZS-0002ev-U9 for qemu-devel@archiver.kernel.org; Tue, 24 May 2022 05:11:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57278) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ntPkz-0006c8-ED for qemu-devel@nongnu.org; Tue, 24 May 2022 04:19:10 -0400 Received: from mail.loongson.cn ([114.242.206.163]:47474 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ntPkq-0002FV-Ru for qemu-devel@nongnu.org; Tue, 24 May 2022 04:19:08 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Axqti8lIxi2v8gAA--.27451S31; Tue, 24 May 2022 16:18:41 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca Subject: [PATCH v5 29/43] target/loongarch: Add timer related instructions support. Date: Tue, 24 May 2022 16:17:50 +0800 Message-Id: <20220524081804.3608101-30-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220524081804.3608101-1-yangxiaojuan@loongson.cn> References: <20220524081804.3608101-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Axqti8lIxi2v8gAA--.27451S31 X-Coremail-Antispam: 1UD129KBjvJXoWxGry8AryfXFy5Kr43Aw4UXFb_yoWrtr4fpr 4I9ryUKrW8JrZxZwn3K3s8Xr15Xw4xCF42qa93t3s5CF47X3Z7Zr18t3sxKF4UJw4DXryj qF1kA34jkFWxXaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This includes: -RDTIME{L/H}.W -RDTIME.D Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/disas.c | 3 ++ target/loongarch/helper.h | 2 ++ target/loongarch/insn_trans/trans_extra.c.inc | 33 +++++++++++++++++++ target/loongarch/insns.decode | 3 ++ target/loongarch/op_helper.c | 13 ++++++++ target/loongarch/translate.c | 2 ++ 6 files changed, 56 insertions(+) diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 9d790b172c..858dfcc53a 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -352,6 +352,9 @@ INSN(bitrev_w, rr) INSN(bitrev_d, rr) INSN(ext_w_h, rr) INSN(ext_w_b, rr) +INSN(rdtimel_w, rr) +INSN(rdtimeh_w, rr) +INSN(rdtime_d, rr) INSN(cpucfg, rr) INSN(asrtle_d, rr_jk) INSN(asrtgt_d, rr_jk) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index 626fc32e1e..85c11a60d4 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -93,6 +93,8 @@ DEF_HELPER_2(frint_d, i64, env, i64) DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_1(rdtime_d, i64, env) + /* CSRs helper */ DEF_HELPER_1(csrrd_pgd, i64, env) DEF_HELPER_1(csrrd_tval, i64, env) diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc index 549f75a867..ad713cd61e 100644 --- a/target/loongarch/insn_trans/trans_extra.c.inc +++ b/target/loongarch/insn_trans/trans_extra.c.inc @@ -33,6 +33,39 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a) return true; } +static bool gen_rdtime(DisasContext *ctx, arg_rr *a, + bool word, bool high) +{ + TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE); + TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE); + + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_rdtime_d(dst1, cpu_env); + if (word) { + tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32); + } + tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TID)); + + return true; +} + +static bool trans_rdtimel_w(DisasContext *ctx, arg_rdtimel_w *a) +{ + return gen_rdtime(ctx, a, 1, 0); +} + +static bool trans_rdtimeh_w(DisasContext *ctx, arg_rdtimeh_w *a) +{ + return gen_rdtime(ctx, a, 1, 1); +} + +static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a) +{ + return gen_rdtime(ctx, a, 0, 0); +} + static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index ebd3d505fb..3fdc6e148c 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -309,6 +309,9 @@ break 0000 00000010 10100 ............... @i15 syscall 0000 00000010 10110 ............... @i15 asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk +rdtimel_w 0000 00000000 00000 11000 ..... ..... @rr +rdtimeh_w 0000 00000000 00000 11001 ..... ..... @rr +rdtime_d 0000 00000000 00000 11010 ..... ..... @rr cpucfg 0000 00000000 00000 11011 ..... ..... @rr # diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c index 2243fcfa44..7bd29871ae 100644 --- a/target/loongarch/op_helper.c +++ b/target/loongarch/op_helper.c @@ -84,6 +84,19 @@ target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj) return rj > 21 ? 0 : env->cpucfg[rj]; } +uint64_t helper_rdtime_d(CPULoongArchState *env) +{ + uint64_t plv; + LoongArchCPU *cpu = env_archcpu(env); + + plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + if (extract64(env->CSR_MISC, R_CSR_MISC_DRDTL_SHIFT + plv, 1)) { + do_raise_exception(env, EXCCODE_IPE, GETPC()); + } + + return cpu_loongarch_get_constant_timer_counter(cpu); +} + void helper_ertn(CPULoongArchState *env) { uint64_t csr_pplv, csr_pie; diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 82694f487f..c1f72ee153 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -25,6 +25,8 @@ static TCGv cpu_lladdr, cpu_llval; TCGv_i32 cpu_fcsr0; TCGv_i64 cpu_fpr[32]; +#include "exec/gen-icount.h" + #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 #define DISAS_EXIT_UPDATE DISAS_TARGET_2