[v5,41/43] target/loongarch: Add gdb support.

Message ID	20220524081804.3608101-42-yangxiaojuan@loongson.cn (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Xiaojuan Yang <yangxiaojuan@loongson.cn> To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca Subject: [PATCH v5 41/43] target/loongarch: Add gdb support. Date: Tue, 24 May 2022 16:18:02 +0800 Message-Id: <20220524081804.3608101-42-yangxiaojuan@loongson.cn> In-Reply-To: <20220524081804.3608101-1-yangxiaojuan@loongson.cn> References: <20220524081804.3608101-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	Add LoongArch softmmu support \| expand [v5,00/43] Add LoongArch softmmu support [v5,01/43] target/loongarch: Add README [v5,02/43] target/loongarch: Add core definition [v5,03/43] target/loongarch: Add main translation routines [v5,04/43] target/loongarch: Add fixed point arithmetic instruction translation [v5,05/43] target/loongarch: Add fixed point shift instruction translation [v5,06/43] target/loongarch: Add fixed point bit instruction translation [v5,07/43] target/loongarch: Add fixed point load/store instruction translation [v5,08/43] target/loongarch: Add fixed point atomic instruction translation [v5,09/43] target/loongarch: Add fixed point extra instruction translation [v5,10/43] target/loongarch: Add floating point arithmetic instruction translation [v5,11/43] target/loongarch: Add floating point comparison instruction translation [v5,12/43] target/loongarch: Add floating point conversion instruction translation [v5,13/43] target/loongarch: Add floating point move instruction translation [v5,14/43] target/loongarch: Add floating point load/store instruction translation [v5,15/43] target/loongarch: Add branch instruction translation [v5,16/43] target/loongarch: Add disassembler [v5,17/43] target/loongarch: Add target build suport [v5,18/43] target/loongarch: Add system emulation introduction [v5,19/43] target/loongarch: Add CSRs definition [v5,20/43] target/loongarch: Add basic vmstate description of CPU. [v5,21/43] target/loongarch: Implement qmp_query_cpu_definitions() [v5,22/43] target/loongarch: Add MMU support for LoongArch CPU. [v5,23/43] target/loongarch: Add LoongArch interrupt and exception handle [v5,24/43] target/loongarch: Add constant timer support [v5,25/43] target/loongarch: Add LoongArch CSR instruction [v5,26/43] target/loongarch: Add LoongArch IOCSR instruction [v5,27/43] target/loongarch: Add TLB instruction support [v5,28/43] target/loongarch: Add other core instructions support [v5,29/43] target/loongarch: Add timer related instructions support. [v5,30/43] hw/loongarch: Add support loongson3 virt machine type. [v5,31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) [v5,32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) [v5,33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) [v5,34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) [v5,35/43] hw/loongarch: Add irq hierarchy for the system [v5,36/43] Enable common virtio pci support for LoongArch [v5,37/43] hw/loongarch: Add some devices support for 3A5000. [v5,38/43] hw/loongarch: Add LoongArch ls7a rtc device support [v5,39/43] hw/loongarch: Add LoongArch load elf function. [v5,40/43] hw/loongarch: Add LoongArch ls7a acpi device support [v5,41/43] target/loongarch: Add gdb support. [v5,42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system [v5,43/43] target/loongarch: 'make check-tcg' support

diff --git a/MAINTAINERS b/MAINTAINERS index 6f861dec0a..806813e487 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1140,6 +1140,7 @@ F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c F: include/hw/acpi/ls7a.h F: hw/acpi/ls7a.c +F: gdb-xml/loongarch*.xml M68K Machines ------------- diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak index 666154022f..7bc06c850c 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=loongarch64 TARGET_BASE_ARCH=loongarch TARGET_SUPPORTS_MTTCG=y +TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml diff --git a/gdb-xml/loongarch-base64.xml b/gdb-xml/loongarch-base64.xml new file mode 100644 index 0000000000..4962bdbd28 --- /dev/null +++ b/gdb-xml/loongarch-base64.xml @@ -0,0 +1,44 @@ +<?xml version="1.0"?> + + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.loongarch.base"> + <reg name="r0" bitsize="64" type="uint64" group="general"/> + <reg name="r1" bitsize="64" type="uint64" group="general"/> + <reg name="r2" bitsize="64" type="uint64" group="general"/> + <reg name="r3" bitsize="64" type="uint64" group="general"/> + <reg name="r4" bitsize="64" type="uint64" group="general"/> + <reg name="r5" bitsize="64" type="uint64" group="general"/> + <reg name="r6" bitsize="64" type="uint64" group="general"/> + <reg name="r7" bitsize="64" type="uint64" group="general"/> + <reg name="r8" bitsize="64" type="uint64" group="general"/> + <reg name="r9" bitsize="64" type="uint64" group="general"/> + <reg name="r10" bitsize="64" type="uint64" group="general"/> + <reg name="r11" bitsize="64" type="uint64" group="general"/> + <reg name="r12" bitsize="64" type="uint64" group="general"/> + <reg name="r13" bitsize="64" type="uint64" group="general"/> + <reg name="r14" bitsize="64" type="uint64" group="general"/> + <reg name="r15" bitsize="64" type="uint64" group="general"/> + <reg name="r16" bitsize="64" type="uint64" group="general"/> + <reg name="r17" bitsize="64" type="uint64" group="general"/> + <reg name="r18" bitsize="64" type="uint64" group="general"/> + <reg name="r19" bitsize="64" type="uint64" group="general"/> + <reg name="r20" bitsize="64" type="uint64" group="general"/> + <reg name="r21" bitsize="64" type="uint64" group="general"/> + <reg name="r22" bitsize="64" type="uint64" group="general"/> + <reg name="r23" bitsize="64" type="uint64" group="general"/> + <reg name="r24" bitsize="64" type="uint64" group="general"/> + <reg name="r25" bitsize="64" type="uint64" group="general"/> + <reg name="r26" bitsize="64" type="uint64" group="general"/> + <reg name="r27" bitsize="64" type="uint64" group="general"/> + <reg name="r28" bitsize="64" type="uint64" group="general"/> + <reg name="r29" bitsize="64" type="uint64" group="general"/> + <reg name="r30" bitsize="64" type="uint64" group="general"/> + <reg name="r31" bitsize="64" type="uint64" group="general"/> + <reg name="pc" bitsize="64" type="code_ptr" group="general"/> + <reg name="badvaddr" bitsize="64" type="code_ptr" group="general"/> +</feature> diff --git a/gdb-xml/loongarch-fpu64.xml b/gdb-xml/loongarch-fpu64.xml new file mode 100644 index 0000000000..e52cf89fbc --- /dev/null +++ b/gdb-xml/loongarch-fpu64.xml @@ -0,0 +1,57 @@ +<?xml version="1.0"?> + + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.loongarch.fpu"> + + <union id="fpu64type"> + <field name="f" type="ieee_single"/> + <field name="d" type="ieee_double"/> + </union> + + <reg name="f0" bitsize="64" type="fpu64type" group="float"/> + <reg name="f1" bitsize="64" type="fpu64type" group="float"/> + <reg name="f2" bitsize="64" type="fpu64type" group="float"/> + <reg name="f3" bitsize="64" type="fpu64type" group="float"/> + <reg name="f4" bitsize="64" type="fpu64type" group="float"/> + <reg name="f5" bitsize="64" type="fpu64type" group="float"/> + <reg name="f6" bitsize="64" type="fpu64type" group="float"/> + <reg name="f7" bitsize="64" type="fpu64type" group="float"/> + <reg name="f8" bitsize="64" type="fpu64type" group="float"/> + <reg name="f9" bitsize="64" type="fpu64type" group="float"/> + <reg name="f10" bitsize="64" type="fpu64type" group="float"/> + <reg name="f11" bitsize="64" type="fpu64type" group="float"/> + <reg name="f12" bitsize="64" type="fpu64type" group="float"/> + <reg name="f13" bitsize="64" type="fpu64type" group="float"/> + <reg name="f14" bitsize="64" type="fpu64type" group="float"/> + <reg name="f15" bitsize="64" type="fpu64type" group="float"/> + <reg name="f16" bitsize="64" type="fpu64type" group="float"/> + <reg name="f17" bitsize="64" type="fpu64type" group="float"/> + <reg name="f18" bitsize="64" type="fpu64type" group="float"/> + <reg name="f19" bitsize="64" type="fpu64type" group="float"/> + <reg name="f20" bitsize="64" type="fpu64type" group="float"/> + <reg name="f21" bitsize="64" type="fpu64type" group="float"/> + <reg name="f22" bitsize="64" type="fpu64type" group="float"/> + <reg name="f23" bitsize="64" type="fpu64type" group="float"/> + <reg name="f24" bitsize="64" type="fpu64type" group="float"/> + <reg name="f25" bitsize="64" type="fpu64type" group="float"/> + <reg name="f26" bitsize="64" type="fpu64type" group="float"/> + <reg name="f27" bitsize="64" type="fpu64type" group="float"/> + <reg name="f28" bitsize="64" type="fpu64type" group="float"/> + <reg name="f29" bitsize="64" type="fpu64type" group="float"/> + <reg name="f30" bitsize="64" type="fpu64type" group="float"/> + <reg name="f31" bitsize="64" type="fpu64type" group="float"/> + <reg name="fcc0" bitsize="8" type="uint8" group="float"/> + <reg name="fcc1" bitsize="8" type="uint8" group="float"/> + <reg name="fcc2" bitsize="8" type="uint8" group="float"/> + <reg name="fcc3" bitsize="8" type="uint8" group="float"/> + <reg name="fcc4" bitsize="8" type="uint8" group="float"/> + <reg name="fcc5" bitsize="8" type="uint8" group="float"/> + <reg name="fcc6" bitsize="8" type="uint8" group="float"/> + <reg name="fcc7" bitsize="8" type="uint8" group="float"/> + <reg name="fcsr" bitsize="32" type="uint32" group="float"/> +</feature> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 98dbb266a1..4624679b10 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -482,6 +482,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) return; } + loongarch_cpu_register_gdb_regs_for_features(cs); + cpu_reset(cs); qemu_init_vcpu(cs); @@ -635,6 +637,13 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) dc->vmsd = &vmstate_loongarch_cpu; cc->sysemu_ops = &loongarch_sysemu_ops; cc->disas_set_info = loongarch_cpu_disas_set_info; + cc->gdb_read_register = loongarch_cpu_gdb_read_register; + cc->gdb_write_register = loongarch_cpu_gdb_write_register; + cc->disas_set_info = loongarch_cpu_disas_set_info; + cc->gdb_num_core_regs = 34; + cc->gdb_core_xml_file = "loongarch-base64.xml"; + cc->gdb_stop_before_watchpoint = true; + #ifdef CONFIG_TCG cc->tcg_ops = &loongarch_tcg_ops; #endif diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c new file mode 100644 index 0000000000..0c48834201 --- /dev/null +++ b/target/loongarch/gdbstub.c @@ -0,0 +1,81 @@ +/* + * LOONGARCH gdb server stub + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/gdbstub.h" + +int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; + + if (0 <= n && n < 32) { + return gdb_get_regl(mem_buf, env->gpr[n]); + } else if (n == 32) { + return gdb_get_regl(mem_buf, env->pc); + } else if (n == 33) { + return gdb_get_regl(mem_buf, env->badaddr); + } + return 0; +} + +int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + CPULoongArchState *env = &cpu->env; + target_ulong tmp = ldtul_p(mem_buf); + int length = 0; + + if (0 <= n && n < 32) { + env->gpr[n] = tmp; + length = sizeof(target_ulong); + } else if (n == 32) { + env->pc = tmp; + length = sizeof(target_ulong); + } + return length; +} + +static int loongarch_gdb_get_fpu(CPULoongArchState *env, + GByteArray *mem_buf, int n) +{ + if (0 <= n && n < 32) { + return gdb_get_reg64(mem_buf, env->fpr[n]); + } else if (32 <= n && n < 40) { + return gdb_get_reg8(mem_buf, env->cf[n - 32]); + } else if (n == 40) { + return gdb_get_reg32(mem_buf, env->fcsr0); + } + return 0; +} + +static int loongarch_gdb_set_fpu(CPULoongArchState *env, + uint8_t *mem_buf, int n) +{ + int length = 0; + + if (0 <= n && n < 32) { + env->fpr[n] = ldq_p(mem_buf); + length = 8; + } else if (32 <= n && n < 40) { + env->cf[n - 32] = ldub_p(mem_buf); + length = 1; + } else if (n == 40) { + env->fcsr0 = ldl_p(mem_buf); + length = 4; + } + return length; +} + +void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs) +{ + gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu, + 41, "loongarch-fpu64.xml", 0); +} diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index a410c41c37..9d50fbdd81 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -49,4 +49,8 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n); +int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n); +void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs); + #endif diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build index 74e5f3b2a7..6376f9e84b 100644 --- a/target/loongarch/meson.build +++ b/target/loongarch/meson.build @@ -11,6 +11,7 @@ loongarch_tcg_ss.add(files( 'fpu_helper.c', 'op_helper.c', 'translate.c', + 'gdbstub.c', )) loongarch_tcg_ss.add(zlib)

[v5,41/43] target/loongarch: Add gdb support.

Commit Message

Patch