[v7,30/43] hw/loongarch: Add support loongson3 virt machine type.

Message ID	20220606124333.2060567-31-yangxiaojuan@loongson.cn (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Xiaojuan Yang <yangxiaojuan@loongson.cn> To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, maobibo@loongson.cn Subject: [PATCH v7 30/43] hw/loongarch: Add support loongson3 virt machine type. Date: Mon, 6 Jun 2022 20:43:20 +0800 Message-Id: <20220606124333.2060567-31-yangxiaojuan@loongson.cn> In-Reply-To: <20220606124333.2060567-1-yangxiaojuan@loongson.cn> References: <20220606124333.2060567-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	Add LoongArch softmmu support \| expand [v7,00/43] Add LoongArch softmmu support [v7,01/43] target/loongarch: Add README [v7,02/43] target/loongarch: Add core definition [v7,03/43] target/loongarch: Add main translation routines [v7,04/43] target/loongarch: Add fixed point arithmetic instruction translation [v7,05/43] target/loongarch: Add fixed point shift instruction translation [v7,06/43] target/loongarch: Add fixed point bit instruction translation [v7,07/43] target/loongarch: Add fixed point load/store instruction translation [v7,08/43] target/loongarch: Add fixed point atomic instruction translation [v7,09/43] target/loongarch: Add fixed point extra instruction translation [v7,10/43] target/loongarch: Add floating point arithmetic instruction translation [v7,11/43] target/loongarch: Add floating point comparison instruction translation [v7,12/43] target/loongarch: Add floating point conversion instruction translation [v7,13/43] target/loongarch: Add floating point move instruction translation [v7,14/43] target/loongarch: Add floating point load/store instruction translation [v7,15/43] target/loongarch: Add branch instruction translation [v7,16/43] target/loongarch: Add disassembler [v7,17/43] target/loongarch: Add target build suport [v7,18/43] target/loongarch: Add system emulation introduction [v7,19/43] target/loongarch: Add CSRs definition [v7,20/43] target/loongarch: Add basic vmstate description of CPU. [v7,21/43] target/loongarch: Implement qmp_query_cpu_definitions() [v7,22/43] target/loongarch: Add MMU support for LoongArch CPU. [v7,23/43] target/loongarch: Add LoongArch interrupt and exception handle [v7,24/43] target/loongarch: Add constant timer support [v7,25/43] target/loongarch: Add LoongArch CSR instruction [v7,26/43] target/loongarch: Add LoongArch IOCSR instruction [v7,27/43] target/loongarch: Add TLB instruction support [v7,28/43] target/loongarch: Add other core instructions support [v7,29/43] target/loongarch: Add timer related instructions support. [v7,30/43] hw/loongarch: Add support loongson3 virt machine type. [v7,31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) [v7,32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) [v7,33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) [v7,34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) [v7,35/43] hw/loongarch: Add irq hierarchy for the system [v7,36/43] Enable common virtio pci support for LoongArch [v7,37/43] hw/loongarch: Add some devices support for 3A5000. [v7,38/43] hw/loongarch: Add LoongArch ls7a rtc device support [v7,39/43] hw/loongarch: Add LoongArch load elf function. [v7,40/43] hw/loongarch: Add LoongArch virt power manager support. [v7,41/43] target/loongarch: Add gdb support. [v7,42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system [v7,43/43] target/loongarch: 'make check-tcg' support

diff --git a/MAINTAINERS b/MAINTAINERS index e3f875071a..0c54c03cef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1129,6 +1129,10 @@ M: Xiaojuan Yang <yangxiaojuan@loongson.cn> M: Song Gao <gaosong@loongson.cn> S: Maintained F: docs/system/loongarch/loongson3.rst +F: configs/targets/loongarch64-softmmu.mak +F: configs/devices/loongarch64-softmmu/default.mak +F: hw/loongarch/ +F: include/hw/loongarch/virt.h M68K Machines ------------- diff --git a/configs/devices/loongarch64-softmmu/default.mak b/configs/devices/loongarch64-softmmu/default.mak new file mode 100644 index 0000000000..928bc117ef --- /dev/null +++ b/configs/devices/loongarch64-softmmu/default.mak @@ -0,0 +1,3 @@ +# Default configuration for loongarch64-softmmu + +CONFIG_LOONGARCH_VIRT=y diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak new file mode 100644 index 0000000000..666154022f --- /dev/null +++ b/configs/targets/loongarch64-softmmu.mak @@ -0,0 +1,3 @@ +TARGET_ARCH=loongarch64 +TARGET_BASE_ARCH=loongarch +TARGET_SUPPORTS_MTTCG=y diff --git a/hw/Kconfig b/hw/Kconfig index 50e0952889..38233bbb0f 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -50,6 +50,7 @@ source avr/Kconfig source cris/Kconfig source hppa/Kconfig source i386/Kconfig +source loongarch/Kconfig source m68k/Kconfig source microblaze/Kconfig source mips/Kconfig diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig new file mode 100644 index 0000000000..13e8501897 --- /dev/null +++ b/hw/loongarch/Kconfig @@ -0,0 +1,4 @@ +config LOONGARCH_VIRT + bool + select PCI + select PCI_EXPRESS_GENERIC_BRIDGE diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c new file mode 100644 index 0000000000..7df32f777e --- /dev/null +++ b/hw/loongarch/loongson3.c @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU loongson 3a5000 develop board emulation + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + */ +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/datadir.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "sysemu/sysemu.h" +#include "sysemu/qtest.h" +#include "sysemu/runstate.h" +#include "sysemu/reset.h" +#include "sysemu/rtc.h" +#include "hw/loongarch/virt.h" +#include "exec/address-spaces.h" +#include "target/loongarch/cpu.h" + +static void loongarch_init(MachineState *machine) +{ + const char *cpu_model = machine->cpu_type; + ram_addr_t offset = 0; + ram_addr_t ram_size = machine->ram_size; + uint64_t highram_size = 0; + MemoryRegion *address_space_mem = get_system_memory(); + LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); + int i; + + if (!cpu_model) { + cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); + } + + if (!strstr(cpu_model, "la464")) { + error_report("LoongArch/TCG needs cpu type la464"); + exit(1); + } + + if (ram_size < 1 * GiB) { + error_report("ram_size must be greater than 1G."); + exit(1); + } + + /* Init CPUs */ + for (i = 0; i < machine->smp.cpus; i++) { + cpu_create(machine->cpu_type); + } + + /* Add memory region */ + memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", + machine->ram, 0, 256 * MiB); + memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); + offset += 256 * MiB; + + highram_size = ram_size - 256 * MiB; + memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", + machine->ram, offset, highram_size); + memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem); + + /* Add isa io region */ + memory_region_init_alias(&lams->isa_io, NULL, "isa-io", + get_system_io(), 0, LOONGARCH_ISA_IO_SIZE); + memory_region_add_subregion(address_space_mem, LOONGARCH_ISA_IO_BASE, + &lams->isa_io); +} + +static void loongarch_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "Loongson-3A5000 LS7A1000 machine"; + mc->init = loongarch_init; + mc->default_ram_size = 1 * GiB; + mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); + mc->default_ram_id = "loongarch.ram"; + mc->max_cpus = LOONGARCH_MAX_VCPUS; + mc->is_default = 1; + mc->default_kernel_irqchip_split = false; + mc->block_default_type = IF_VIRTIO; + mc->default_boot_order = "c"; + mc->no_cdrom = 1; +} + +static const TypeInfo loongarch_machine_types[] = { + { + .name = TYPE_LOONGARCH_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(LoongArchMachineState), + .class_init = loongarch_class_init, + } +}; + +DEFINE_TYPES(loongarch_machine_types) diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build new file mode 100644 index 0000000000..cecb1a5d65 --- /dev/null +++ b/hw/loongarch/meson.build @@ -0,0 +1,4 @@ +loongarch_ss = ss.source_set() +loongarch_ss.add(when: 'CONFIG_LOONGARCH_VIRT', if_true: files('loongson3.c')) + +hw_arch += {'loongarch': loongarch_ss} diff --git a/hw/meson.build b/hw/meson.build index 9992c5101e..c7ac7d3d75 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -50,6 +50,7 @@ subdir('avr') subdir('cris') subdir('hppa') subdir('i386') +subdir('loongarch') subdir('m68k') subdir('microblaze') subdir('mips') diff --git a/include/exec/poison.h b/include/exec/poison.h index 9f1ca3409c..bbb82cf9ec 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -14,6 +14,7 @@ #pragma GCC poison TARGET_CRIS #pragma GCC poison TARGET_HEXAGON #pragma GCC poison TARGET_HPPA +#pragma GCC poison TARGET_LOONGARCH64 #pragma GCC poison TARGET_M68K #pragma GCC poison TARGET_MICROBLAZE #pragma GCC poison TARGET_MIPS @@ -71,6 +72,7 @@ #pragma GCC poison CONFIG_HPPA_DIS #pragma GCC poison CONFIG_I386_DIS #pragma GCC poison CONFIG_HEXAGON_DIS +#pragma GCC poison CONFIG_LOONGARCH_DIS #pragma GCC poison CONFIG_M68K_DIS #pragma GCC poison CONFIG_MICROBLAZE_DIS #pragma GCC poison CONFIG_MIPS_DIS diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h new file mode 100644 index 0000000000..4a4bb3f51f --- /dev/null +++ b/include/hw/loongarch/virt.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Definitions for loongarch board emulation. + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGARCH_H +#define HW_LOONGARCH_H + +#include "target/loongarch/cpu.h" +#include "hw/boards.h" +#include "qemu/queue.h" + +#define LOONGARCH_MAX_VCPUS 4 + +#define LOONGARCH_ISA_IO_BASE 0x18000000UL +#define LOONGARCH_ISA_IO_SIZE 0x0004000 + +struct LoongArchMachineState { + /*< private >*/ + MachineState parent_obj; + + MemoryRegion lowmem; + MemoryRegion highmem; + MemoryRegion isa_io; +}; + +#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt") +OBJECT_DECLARE_SIMPLE_TYPE(LoongArchMachineState, LOONGARCH_MACHINE) +#endif diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 79c2591425..8850cb1a14 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -24,6 +24,7 @@ enum { QEMU_ARCH_RX = (1 << 20), QEMU_ARCH_AVR = (1 << 21), QEMU_ARCH_HEXAGON = (1 << 22), + QEMU_ARCH_LOONGARCH = (1 << 23), }; extern const uint32_t arch_type; diff --git a/qapi/machine.json b/qapi/machine.json index 883ce3f9ea..f750a16396 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -30,7 +30,7 @@ ## { 'enum' : 'SysEmuTarget', 'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386', - 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64', + 'loongarch64', 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64', 'mips64el', 'mipsel', 'nios2', 'or1k', 'ppc', 'ppc64', 'riscv32', 'riscv64', 'rx', 's390x', 'sh4', 'sh4eb', 'sparc', 'sparc64', 'tricore', diff --git a/target/Kconfig b/target/Kconfig index ae7f24fc66..83da0bd293 100644 --- a/target/Kconfig +++ b/target/Kconfig @@ -4,6 +4,7 @@ source avr/Kconfig source cris/Kconfig source hppa/Kconfig source i386/Kconfig +source loongarch/Kconfig source m68k/Kconfig source microblaze/Kconfig source mips/Kconfig diff --git a/target/loongarch/Kconfig b/target/loongarch/Kconfig new file mode 100644 index 0000000000..46b26b1a85 --- /dev/null +++ b/target/loongarch/Kconfig @@ -0,0 +1,2 @@ +config LOONGARCH64 + bool diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b846bd1a8b..3b7d6289d2 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -82,6 +82,8 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) env->pc = value; } +#include "hw/loongarch/virt.h" + void loongarch_cpu_set_irq(void *opaque, int irq, int level) { LoongArchCPU *cpu = opaque;

[v7,30/43] hw/loongarch: Add support loongson3 virt machine type.

Commit Message

Patch