diff mbox series

[2/6] target/riscv: H extension depends on I extension

Message ID 20220710082400.29224-3-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series Improve the U/S/H extension related check | expand

Commit Message

Weiwei Li July 10, 2022, 8:23 a.m. UTC 
- add check for "H depends on an I base integer ISA with 32 x registers"

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Alistair Francis July 11, 2022, 5:29 a.m. UTC | #1 
On Sun, Jul 10, 2022 at 6:24 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - add check for "H depends on an I base integer ISA with 32 x registers"
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0dad6906bc..4e40f26e13 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -642,6 +642,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>              return;
>          }
>
> +        if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
> +            error_setg(errp,
> +                       "H depends on an I base integer ISA with 32 x registers");
> +            return;
> +        }
> +
>          if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
>              error_setg(errp, "F extension requires Zicsr");
>              return;
> --
> 2.17.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dad6906bc..4e40f26e13 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -642,6 +642,12 @@  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             return;
         }
 
+        if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
+            error_setg(errp,
+                       "H depends on an I base integer ISA with 32 x registers");
+            return;
+        }
+
         if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
             error_setg(errp, "F extension requires Zicsr");
             return;