| Message ID | 20220710082400.29224-5-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Improve the U/S/H extension related check | expand |
On Sun, Jul 10, 2022 at 6:28 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > - add umode/umode32 predicate for mcounteren,menvcfg/menvcfgh > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/csr.c | 25 ++++++++++++++++++++++--- > 1 file changed, 22 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 9bda1ff993..0d8e98b7a9 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -339,6 +339,25 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) > > } > > +static RISCVException umode(CPURISCVState *env, int csrno) > +{ > + if (riscv_has_ext(env, RVU)) { > + /* User extension is supported */ > + return RISCV_EXCP_NONE; > + } > + > + return RISCV_EXCP_ILLEGAL_INST; > +} > + > +static RISCVException umode32(CPURISCVState *env, int csrno) > +{ > + if (riscv_cpu_mxl(env) != MXL_RV32) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + return umode(env, csrno); > +} > + > /* Checks if PointerMasking registers could be accessed */ > static RISCVException pointer_masking(CPURISCVState *env, int csrno) > { > @@ -3521,7 +3540,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, > [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, > [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, > - [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, > + [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren, > write_mcounteren }, > > [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, > @@ -3554,9 +3573,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, > > /* Execution environment configuration */ > - [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, > + [CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, > + [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > -- > 2.17.1 > >
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9bda1ff993..0d8e98b7a9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -339,6 +339,25 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) } +static RISCVException umode(CPURISCVState *env, int csrno) +{ + if (riscv_has_ext(env, RVU)) { + /* User extension is supported */ + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} + +static RISCVException umode32(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_mxl(env) != MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return umode(env, csrno); +} + /* Checks if PointerMasking registers could be accessed */ static RISCVException pointer_masking(CPURISCVState *env, int csrno) { @@ -3521,7 +3540,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, - [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, + [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren, write_mcounteren }, [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, @@ -3554,9 +3573,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, /* Execution environment configuration */ - [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, + [CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg, .min_priv_ver = PRIV_VERSION_1_12_0 }, - [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, + [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh, .min_priv_ver = PRIV_VERSION_1_12_0 }, [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, .min_priv_ver = PRIV_VERSION_1_12_0 },