diff mbox series

[v2,1/6] target/riscv: add check for supported privilege modes conbinations

Message ID 20220712063236.23834-2-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series Improve the U/S/H extension related check | expand

Commit Message

Weiwei Li July 12, 2022, 6:32 a.m. UTC 
- There are 3 suggested privilege modes conbinations listed in the spec:
1) M, 2) M, U 3) M, S, U

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Weiwei Li July 18, 2022, 11:36 a.m. UTC | #1 
在 2022/7/18 下午5:02, Andrew Jones 写道:
> On Tue, Jul 12, 2022 at 02:32:31PM +0800, Weiwei Li wrote:
>> - There are 3 suggested privilege modes conbinations listed in the spec:
> No need for '-' here.
>
> s/modes/mode/
> s/conbinations/combinations/
>
> (Same typos in $SUBJECT, also please capitalize 'add' in $SUBJECT.)
>
> When referencing the spec it's nice to point out the doc/version/section.
>
>> 1) M, 2) M, U 3) M, S, U
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>>   target/riscv/cpu.c | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index db2b8e4d30..36c1b26fb3 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -726,6 +726,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>>               return;
>>           }
>>   
>> +        if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
>> +            error_setg(errp,
>> +                       "Setting S extension without U extension is illegal");
>> +            return;
>> +        }
>> +
>>           if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
>>               error_setg(errp, "F extension requires Zicsr");
>>               return;
>> -- 
>> 2.17.1
>>
>>
> Besides the commit message issues
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Thanks for your comments.

I'll fix the issues in commit messages in the next version.

Regards,

Weiwei Li
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index db2b8e4d30..36c1b26fb3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -726,6 +726,12 @@  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             return;
         }
 
+        if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
+            error_setg(errp,
+                       "Setting S extension without U extension is illegal");
+            return;
+        }
+
         if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
             error_setg(errp, "F extension requires Zicsr");
             return;