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[5/7] pci: designware: move msi to entry 5

Message ID 20220713165449.37433-6-ben.dooks@sifive.com (mailing list archive)
State New, archived
Headers show
Series [1/7] pci: designware: add 64-bit viewport limit | expand

Commit Message

Ben Dooks July 13, 2022, 4:54 p.m. UTC 
The driver should leave irq[0..3] for INT[A..D] but seems to put the
MSI IRQ at entry 3 which should also be INT_D. Extend the irqs[] array
to 5 entires and put the MSI at entry irqs[4].

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
 hw/pci-host/designware.c         | 2 +-
 include/hw/pci-host/designware.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 947547d153..b5d5b2b8a5 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -56,7 +56,7 @@ 
 #define DESIGNWARE_PCIE_ATU_UPPER_TARGET           0x91C
 #define DESIGNWARE_PCIE_ATU_UPPER_LIMIT            0x924
 
-#define DESIGNWARE_PCIE_IRQ_MSI                    3
+#define DESIGNWARE_PCIE_IRQ_MSI                    4
 
 static DesignwarePCIEHost *
 designware_pcie_root_to_host(DesignwarePCIERoot *root)
diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h
index bd4dd49aec..37f90c5000 100644
--- a/include/hw/pci-host/designware.h
+++ b/include/hw/pci-host/designware.h
@@ -90,7 +90,7 @@  struct DesignwarePCIEHost {
         MemoryRegion memory;
         MemoryRegion io;
 
-        qemu_irq     irqs[4];
+        qemu_irq     irqs[5];
     } pci;
 
     MemoryRegion mmio;