From patchwork Wed Jul 13 16:54:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 12917090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA44AC433EF for ; Wed, 13 Jul 2022 20:48:46 +0000 (UTC) Received: from localhost ([::1]:36198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBjHp-0008Vj-H1 for qemu-devel@archiver.kernel.org; Wed, 13 Jul 2022 16:48:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBfwJ-0006ZZ-P1; Wed, 13 Jul 2022 13:14:19 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]:60716) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBfwI-0003Aa-6c; Wed, 13 Jul 2022 13:14:19 -0400 Received: from cpc152649-stkp13-2-0-cust121.10-2.cable.virginm.net ([86.15.83.122] helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1oBfdU-003M8r-1K; Wed, 13 Jul 2022 17:54:51 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1oBfdS-0009l5-22; Wed, 13 Jul 2022 17:54:50 +0100 From: Ben Dooks To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Jude Onyenegecha , Sudip Mukherjee , William Salmon , Adnan Chowdhury , Ben Dooks Subject: [PATCH 7/7] pci: designware: add initial tracing events Date: Wed, 13 Jul 2022 17:54:49 +0100 Message-Id: <20220713165449.37433-8-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220713165449.37433-1-ben.dooks@sifive.com> References: <20220713165449.37433-1-ben.dooks@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=188.40.203.114; envelope-from=ben@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 13 Jul 2022 16:45:26 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a couple of tracing events for internal driver updates Signed-off-by: Ben Dooks --- hw/pci-host/designware.c | 4 ++++ hw/pci-host/trace-events | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index a47ae48071..489959513f 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -30,6 +30,7 @@ #include "migration/vmstate.h" #include "hw/irq.h" #include "hw/pci-host/designware.h" +#include "trace.h" #define DESIGNWARE_PCIE_PORT_LINK_CONTROL 0x710 #define DESIGNWARE_PCIE_PHY_DEBUG_R1 0x72C @@ -112,6 +113,7 @@ static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root) const uint64_t base = root->msi.base; const bool enable = root->msi.intr[0].enable; + trace_dw_pcie_msi_update(base, enable); memory_region_set_address(mem, base); memory_region_set_enabled(mem, enable); } @@ -279,6 +281,8 @@ static void designware_pcie_update_viewport(DesignwarePCIERoot *root, uint32_t cr0 = viewport->cr[0]; MemoryRegion *current, *other; + trace_dw_pcie_viewport_update(target, base, size, cr0, enabled); + if ((cr0 & 0xFF) == DESIGNWARE_PCIE_ATU_TYPE_MEM) { current = &viewport->mem; other = &viewport->cfg; diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index 437e66ff50..6b064d3c74 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -3,6 +3,10 @@ # bonito.c bonito_spciconf_small_access(uint64_t addr, unsigned size) "PCI config address is smaller then 32-bit, addr: 0x%"PRIx64", size: %u" +# designware.c +dw_pcie_msi_update(uint64_t base, int enable) "base 0x%" PRIx64 " enable %d" +dw_pcie_viewport_update(uint64_t target, uint64_t base, uint64_t limit, uint32_t cr0, int enabled) "target 0x%" PRIx64 " base 0x%" PRIx64 " limit 0x%" PRIx64 " cr0 0x%" PRIx32 " enabled %d" + # grackle.c grackle_set_irq(int irq_num, int level) "set_irq num %d level %d"