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([93.107.66.220]) by smtp.gmail.com with ESMTPSA id t10-20020a5d49ca000000b0021d6dad334bsm4133543wrs.4.2022.08.05.08.54.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 08:54:17 -0700 (PDT) From: Conor Dooley To: Palmer Dabbelt , Alistair Francis , Bin Meng Cc: Rob Herring , Conor Dooley , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-riscv@lists.infradead.org, Palmer Dabbelt Subject: [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings Date: Fri, 5 Aug 2022 16:54:01 +0100 Message-Id: <20220805155405.1504081-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220805155405.1504081-1-mail@conchuod.ie> References: <20220805155405.1504081-1-mail@conchuod.ie> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=mail@conchuod.ie; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 05 Aug 2022 12:00:40 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Palmer Dabbelt The ISA strings we're providing from QEMU aren't actually legal RISC-V ISA strings, as both S and U cannot exist as single-letter extensions and must instead be multi-letter strings. We're still using the ISA strings inside QEMU to track the availiable extensions, so just strip out the S and U extensions when formatting ISA strings. Signed-off-by: Palmer Dabbelt [Conor: rebased on 7.1.0-rc1 & slightly tweaked the commit message] Signed-off-by: Conor Dooley --- target/riscv/cpu.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac6f82ebd0..95fdc03b3d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1122,7 +1122,23 @@ char *riscv_isa_string(RISCVCPU *cpu) char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { - *p++ = qemu_tolower(riscv_single_letter_exts[i]); + char lower = qemu_tolower(riscv_single_letter_exts[i]); + switch (lower) { + case 's': + case 'u': + /* + * The 's' and 'u' letters shouldn't show up in ISA strings as + * they're not extensions, but they should show up in MISA. + * Since we use these letters interally as a pseudo ISA string + * to set MISA it's easier to just strip them out when + * formatting the ISA string. + */ + break; + + default: + *p++ = lower; + break; + } } } *p = '\0';