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[82.27.106.168]) by smtp.gmail.com with ESMTPSA id q11-20020a5d61cb000000b00223b8168b15sm17236411wrv.66.2022.08.24.08.51.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 08:51:24 -0700 (PDT) From: Jean-Philippe Brucker To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, robh+dt@kernel.org, eauger@redhat.com, Jean-Philippe Brucker Subject: [PATCH 09/10] hw/arm/virt: Fix devicetree warnings about the SMMU node Date: Wed, 24 Aug 2022 16:51:13 +0100 Message-Id: <20220824155113.286730-10-jean-philippe@linaro.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220824155113.286730-1-jean-philippe@linaro.org> References: <20220824155113.286730-1-jean-philippe@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=jean-philippe@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" dt-validate reports three issues in the SMMU device-tree node: smmuv3@9050000: $nodename:0: 'smmuv3@9050000' does not match '^iommu@[0-9a-f]*' smmuv3@9050000: interrupt-names: 'oneOf' conditional failed, one must be fixed: ['eventq', 'priq', 'cmdq-sync', 'gerror'] is too long 'combined' was expected 'gerror' was expected 'gerror' is not one of ['cmdq-sync', 'priq'] smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml Fix them by: * changing the node name * reordering the IRQs * removing the clock properties which are not expected for the SMMU node Signed-off-by: Jean-Philippe Brucker --- hw/arm/virt.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 779eb5ea31..de508d5329 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1329,7 +1329,9 @@ static void create_smmu(const VirtMachineState *vms, int i; hwaddr base = vms->memmap[VIRT_SMMU].base; hwaddr size = vms->memmap[VIRT_SMMU].size; - const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; + uint32_t irq_type = GIC_FDT_IRQ_TYPE_SPI; + uint32_t irq_trigger = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; + const char irq_names[] = "eventq\0gerror\0priq\0cmdq-sync"; DeviceState *dev; MachineState *ms = MACHINE(vms); @@ -1348,22 +1350,20 @@ static void create_smmu(const VirtMachineState *vms, qdev_get_gpio_in(vms->gic, irq + i)); } - node = g_strdup_printf("/smmuv3@%" PRIx64, base); + node = g_strdup_printf("/iommu@%" PRIx64, base); qemu_fdt_add_subnode(ms->fdt, node); qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + irq_type, irq + SMMU_IRQ_EVTQ, irq_trigger, + irq_type, irq + SMMU_IRQ_GERROR, irq_trigger, + irq_type, irq + SMMU_IRQ_PRIQ, irq_trigger, + irq_type, irq + SMMU_IRQ_CMD_SYNC, irq_trigger); qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, sizeof(irq_names)); - qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle); - qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk"); qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);