| Message ID | 20220904072607.44275-1-shorne@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes.
On Sun, 4 Sept 2022 at 03:27, Stafford Horne <shorne@gmail.com> wrote: > > The following changes since commit 61fd710b8da8aedcea9b4f197283dc38638e4b60: > > Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-09-02 13:24:28 -0400) > > are available in the Git repository at: > > git@github.com:stffrdhrn/qemu.git tags/pull-or1k-20220904 Hi Stafford, Please update .git/config to separate the push URL from the fetch URL: [remote "github"] url = https://github.com/stffrdhrn/qemu.git pushUrl = git@gitlab.com:stffrdhrn/qemu.git That way future pull requests will include an https URL that allows fetches without ssh or a GitHub account. Thanks! Stefan
The following changes since commit 61fd710b8da8aedcea9b4f197283dc38638e4b60: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-09-02 13:24:28 -0400) are available in the Git repository at: git@github.com:stffrdhrn/qemu.git tags/pull-or1k-20220904 for you to fetch changes up to b14df228d7c4fe6e86e7f8a4998e9ccf4967b678: docs/system: openrisc: Add OpenRISC documentation (2022-09-04 07:02:57 +0100) ---------------------------------------------------------------- OpenRISC updates for 7.2.0 Updates to add the OpenRISC virt plaform to QEMU. Highlights include: - New virt plaform with, virtio and pci bus support - OpenRISC support for MTTCG - Goldfish RTC device endianness is configurable now ---------------------------------------------------------------- Jason A. Donenfeld (1): hw/openrisc: virt: pass random seed to fdt Stafford Horne (10): hw/openrisc: Split re-usable boot time apis out to boot.c target/openrisc: Fix memory reading in debugger goldfish_rtc: Add big-endian property hw/openrisc: Add the OpenRISC virtual machine hw/openrisc: Add PCI bus support to virt hw/openrisc: Initialize timer time at startup target/openrisc: Add interrupted CPU to log target/openrisc: Enable MTTCG target/openrisc: Interrupt handling fixes docs/system: openrisc: Add OpenRISC documentation configs/devices/or1k-softmmu/default.mak | 1 + configs/targets/or1k-softmmu.mak | 1 + docs/system/openrisc/cpu-features.rst | 15 + docs/system/openrisc/emulation.rst | 17 + docs/system/openrisc/or1k-sim.rst | 43 +++ docs/system/openrisc/virt.rst | 50 +++ docs/system/target-openrisc.rst | 71 ++++ docs/system/targets.rst | 1 + hw/m68k/virt.c | 1 + hw/openrisc/Kconfig | 12 + hw/openrisc/boot.c | 116 +++++++ hw/openrisc/cputimer.c | 22 +- hw/openrisc/meson.build | 2 + hw/openrisc/openrisc_sim.c | 106 +----- hw/openrisc/virt.c | 571 +++++++++++++++++++++++++++++++ hw/rtc/goldfish_rtc.c | 37 +- include/hw/openrisc/boot.h | 34 ++ include/hw/rtc/goldfish_rtc.h | 2 + target/openrisc/cpu.c | 1 - target/openrisc/cpu.h | 2 + target/openrisc/interrupt.c | 4 +- target/openrisc/mmu.c | 8 +- target/openrisc/sys_helper.c | 14 +- 23 files changed, 1017 insertions(+), 114 deletions(-) create mode 100644 docs/system/openrisc/cpu-features.rst create mode 100644 docs/system/openrisc/emulation.rst create mode 100644 docs/system/openrisc/or1k-sim.rst create mode 100644 docs/system/openrisc/virt.rst create mode 100644 docs/system/target-openrisc.rst create mode 100644 hw/openrisc/boot.c create mode 100644 hw/openrisc/virt.c create mode 100644 include/hw/openrisc/boot.h Jason A. Donenfeld (1): hw/openrisc: virt: pass random seed to fdt Stafford Horne (10): hw/openrisc: Split re-usable boot time apis out to boot.c target/openrisc: Fix memory reading in debugger goldfish_rtc: Add big-endian property hw/openrisc: Add the OpenRISC virtual machine hw/openrisc: Add PCI bus support to virt hw/openrisc: Initialize timer time at startup target/openrisc: Add interrupted CPU to log target/openrisc: Enable MTTCG target/openrisc: Interrupt handling fixes docs/system: openrisc: Add OpenRISC documentation configs/devices/or1k-softmmu/default.mak | 1 + configs/targets/or1k-softmmu.mak | 1 + docs/system/openrisc/cpu-features.rst | 15 + docs/system/openrisc/emulation.rst | 17 + docs/system/openrisc/or1k-sim.rst | 43 ++ docs/system/openrisc/virt.rst | 50 ++ docs/system/target-openrisc.rst | 71 +++ docs/system/targets.rst | 1 + hw/m68k/virt.c | 1 + hw/openrisc/Kconfig | 12 + hw/openrisc/boot.c | 116 +++++ hw/openrisc/cputimer.c | 22 +- hw/openrisc/meson.build | 2 + hw/openrisc/openrisc_sim.c | 106 +---- hw/openrisc/virt.c | 571 +++++++++++++++++++++++ hw/rtc/goldfish_rtc.c | 37 +- include/hw/openrisc/boot.h | 34 ++ include/hw/rtc/goldfish_rtc.h | 2 + target/openrisc/cpu.c | 1 - target/openrisc/cpu.h | 2 + target/openrisc/interrupt.c | 4 +- target/openrisc/mmu.c | 8 +- target/openrisc/sys_helper.c | 14 +- 23 files changed, 1017 insertions(+), 114 deletions(-) create mode 100644 docs/system/openrisc/cpu-features.rst create mode 100644 docs/system/openrisc/emulation.rst create mode 100644 docs/system/openrisc/or1k-sim.rst create mode 100644 docs/system/openrisc/virt.rst create mode 100644 docs/system/target-openrisc.rst create mode 100644 hw/openrisc/boot.c create mode 100644 hw/openrisc/virt.c create mode 100644 include/hw/openrisc/boot.h