diff mbox series

[RFC,2/8] target/riscv: add support for Zca, Zcf and Zcd extension

Message ID 20220930012345.5248-3-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series support subsets of code size reduction extension | expand

Commit Message

Weiwei Li Sept. 30, 2022, 1:23 a.m. UTC 
Add check for Zca, Zcf and Zcd extensions in decode_opc

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvi.c.inc |  5 +++--
 target/riscv/translate.c                | 23 +++++++++++++++++++++--
 2 files changed, 24 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index c49dbec0eb..d178da89f9 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -56,7 +56,7 @@  static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
 
     gen_set_pc(ctx, cpu_pc);
-    if (!has_ext(ctx, RVC)) {
+    if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
         TCGv t0 = tcg_temp_new();
 
         misaligned = gen_new_label();
@@ -178,7 +178,8 @@  static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
 
     gen_set_label(l); /* branch taken */
 
-    if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+    if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca &&
+        ((ctx->base.pc_next + a->imm) & 0x3)) {
         /* misaligned */
         gen_exception_inst_addr_mis(ctx);
     } else {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index db123da5ec..a257f0123e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -526,7 +526,7 @@  static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 
     /* check misaligned: */
     next_pc = ctx->base.pc_next + imm;
-    if (!has_ext(ctx, RVC)) {
+    if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
         if ((next_pc & 0x3) != 0) {
             gen_exception_inst_addr_mis(ctx);
             return;
@@ -1064,7 +1064,26 @@  static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 
     /* Check for compressed insn */
     if (insn_len(opcode) == 2) {
-        if (!has_ext(ctx, RVC)) {
+        /*
+         * Zca support all of the existing C extension, excluding all
+         * compressed floating point loads and stores
+         * Zcf(RV32 only) support c.flw, c.flwsp, c.fsw, c.fswsp
+         * Zcd support c.fld, c.fldsp, c.fsd, c.fsdsp
+         */
+        if (!(has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca)) {
+            gen_exception_illegal(ctx);
+        } else if ((get_xl_max(ctx) == MXL_RV32) &&
+            !(has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zcf) &&
+            (((opcode & 0xe003) == 0x6000) ||
+             ((opcode & 0xe003) == 0x6002) ||
+             ((opcode & 0xe003) == 0xe000) ||
+             ((opcode & 0xe003) == 0xe002))) {
+            gen_exception_illegal(ctx);
+        } else if (!(has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zcd) &&
+                   (((opcode & 0xe003) == 0x2000) ||
+                    ((opcode & 0xe003) == 0x2002) ||
+                    ((opcode & 0xe003) == 0xa000) ||
+                    ((opcode & 0xe003) == 0xa002))) {
             gen_exception_illegal(ctx);
         } else {
             ctx->opcode = opcode;