From patchwork Fri Oct 21 03:54:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaojuan Yang X-Patchwork-Id: 13014380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E6B8C43217 for ; Fri, 21 Oct 2022 08:17:07 +0000 (UTC) Received: from localhost ([::1] helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olnDF-0003hw-ST for qemu-devel@archiver.kernel.org; Fri, 21 Oct 2022 04:17:06 -0400 Received: from [::1] (helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olmHC-0003Bw-7D for qemu-devel@archiver.kernel.org; Fri, 21 Oct 2022 03:17:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1olmH5-00039V-3s for qemu-devel@nongnu.org; Fri, 21 Oct 2022 03:16:59 -0400 Received: from mail.loongson.cn ([114.242.206.163] helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olmH0-0005fe-Og for qemu-devel@nongnu.org; Fri, 21 Oct 2022 03:16:58 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxHdnsF1JjEk4BAA--.5951S3; Fri, 21 Oct 2022 11:54:20 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxj+DrF1JjtGsCAA--.9655S3; Fri, 21 Oct 2022 11:54:20 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, f4bug@amsat.org, philmd@linaro.org Subject: [PATCH v1 1/3] hw/loongarch: Change FDT base addr to 2 MiB Date: Fri, 21 Oct 2022 11:54:17 +0800 Message-Id: <20221021035419.2632878-2-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221021035419.2632878-1-yangxiaojuan@loongson.cn> References: <20221021035419.2632878-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bxj+DrF1JjtGsCAA--.9655S3 X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjvJXoWxAF45WFykWw13uFyxtw4rGrg_yoW5Xr1DpF 9xuFn3Wr40qrs3Wrn7GF98uF1DArn7Ca42gFW2kw4FkF9rWr1jqrW8A3yqvFy8J395XF4Y vFyvqrWxX3WrJ3DanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bnxFc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4 AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF 7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7 CjxVAFwI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2 zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VCjz48v1sIEY20_WwAm72CE4IkC6x 0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l42xK82IY6x8ErcxF aVAv8VWrMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxV Cjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY 6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6x AIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY 1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7xRE6wZ7UUUUU== X-Gw-Check: d37b32320bdb7537 Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Change FDT base addr to 2 MiB in lowmem region. Since lowmem region starts from 0, FDT base address is located at 2 MiB to avoid NULL pointer access. Signed-off-by: Xiaojuan Yang --- hw/loongarch/virt.c | 18 +++++++++++------- include/hw/loongarch/virt.h | 3 --- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 29df99727d..fe33e7e3e4 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -159,7 +159,6 @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams) 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 2, base_mmio, 2, size_mmio); g_free(nodename); - qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size); } static void fdt_add_irqchip_node(LoongArchMachineState *lams) @@ -689,6 +688,7 @@ static void loongarch_init(MachineState *machine) MemoryRegion *address_space_mem = get_system_memory(); LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); int i; + hwaddr fdt_base; if (!cpu_model) { cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); @@ -793,12 +793,16 @@ static void loongarch_init(MachineState *machine) lams->machine_done.notify = virt_machine_done; qemu_add_machine_init_done_notifier(&lams->machine_done); fdt_add_pcie_node(lams); - - /* load fdt */ - MemoryRegion *fdt_rom = g_new(MemoryRegion, 1); - memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal); - memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom); - rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE); + /* + * Since lowmem region starts from 0, FDT base address is located + * at 2 MiB to avoid NULL pointer access. + * + * Put the FDT into the memory map as a ROM image: this will ensure + * the FDT is copied again upon reset, even if addr points into RAM. + */ + fdt_base = 2 * MiB; + qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); + rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base); } bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 09f1c88ee5..45c383f5a7 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -28,9 +28,6 @@ #define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN) #define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN) -#define VIRT_FDT_BASE 0x1c400000 -#define VIRT_FDT_SIZE 0x100000 - struct LoongArchMachineState { /*< private >*/ MachineState parent_obj;