diff mbox series

[6/6] target/mips: Make MXU decoder standalone

Message ID 20221024152349.215135-7-jiaxun.yang@flygoat.com (mailing list archive)
State New, archived
Headers show
Series MIPS decodetree conversion | expand

Commit Message

Jiaxun Yang Oct. 24, 2022, 3:23 p.m. UTC 
MXU is treated as an ISA extension for now.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/mips/tcg/mxu_translate.c | 98 ++++++++++++++++++---------------
 target/mips/tcg/translate.c     | 13 ++---
 2 files changed, 60 insertions(+), 51 deletions(-)
diff mbox series

Patch

diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index f52244e1b2..9be37da620 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -354,6 +354,8 @@ 
  *   Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2, 2017
  */
 
+#define OPC_SPECIAL2 (0x1C << 26)
+
 enum {
     OPC_MXU__POOL00  = 0x03,
     OPC_MXU_D16MUL   = 0x08,
@@ -1552,54 +1554,64 @@  bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
 {
     uint32_t opcode = extract32(insn, 0, 6);
 
-    if (opcode == OPC_MXU_S32M2I) {
-        gen_mxu_s32m2i(ctx);
-        return true;
+    if (MASK_OP_MAJOR(insn) != OPC_SPECIAL2) {
+        return false;
     }
 
-    if (opcode == OPC_MXU_S32I2M) {
+    switch (opcode) {
+    case OPC_MXU_S32M2I:
+        gen_mxu_s32m2i(ctx);
+        return true;
+    case OPC_MXU_S32I2M:
         gen_mxu_s32i2m(ctx);
         return true;
-    }
-
-    {
-        TCGv t_mxu_cr = tcg_temp_new();
-        TCGLabel *l_exit = gen_new_label();
-
-        gen_load_mxu_cr(t_mxu_cr);
-        tcg_gen_andi_tl(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN);
-        tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit);
+    case OPC_MXU__POOL00:
+    case OPC_MXU_D16MUL:
+    case OPC_MXU_D16MAC:
+    case OPC_MXU__POOL04:
+    case OPC_MXU_S8LDD:
+    case OPC_MXU__POOL16:
+    case OPC_MXU__POOL19:
+        {
+            TCGv t_mxu_cr = tcg_temp_new();
+            TCGLabel *l_exit = gen_new_label();
+
+            gen_load_mxu_cr(t_mxu_cr);
+            tcg_gen_andi_tl(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN);
+            tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit);
+
+            switch (opcode) {
+            case OPC_MXU__POOL00:
+                decode_opc_mxu__pool00(ctx);
+                break;
+            case OPC_MXU_D16MUL:
+                gen_mxu_d16mul(ctx);
+                break;
+            case OPC_MXU_D16MAC:
+                gen_mxu_d16mac(ctx);
+                break;
+            case OPC_MXU__POOL04:
+                decode_opc_mxu__pool04(ctx);
+                break;
+            case OPC_MXU_S8LDD:
+                gen_mxu_s8ldd(ctx);
+                break;
+            case OPC_MXU__POOL16:
+                decode_opc_mxu__pool16(ctx);
+                break;
+            case OPC_MXU__POOL19:
+                decode_opc_mxu__pool19(ctx);
+                break;
+            default:
+                MIPS_INVAL("decode_opc_mxu");
+                gen_reserved_instruction(ctx);
+            }
 
-        switch (opcode) {
-        case OPC_MXU__POOL00:
-            decode_opc_mxu__pool00(ctx);
-            break;
-        case OPC_MXU_D16MUL:
-            gen_mxu_d16mul(ctx);
-            break;
-        case OPC_MXU_D16MAC:
-            gen_mxu_d16mac(ctx);
-            break;
-        case OPC_MXU__POOL04:
-            decode_opc_mxu__pool04(ctx);
-            break;
-        case OPC_MXU_S8LDD:
-            gen_mxu_s8ldd(ctx);
-            break;
-        case OPC_MXU__POOL16:
-            decode_opc_mxu__pool16(ctx);
-            break;
-        case OPC_MXU__POOL19:
-            decode_opc_mxu__pool19(ctx);
-            break;
-        default:
-            MIPS_INVAL("decode_opc_mxu");
-            gen_reserved_instruction(ctx);
+            gen_set_label(l_exit);
+            tcg_temp_free(t_mxu_cr);
         }
-
-        gen_set_label(l_exit);
-        tcg_temp_free(t_mxu_cr);
+        return true;
+    default:
+        return false;
     }
-
-    return true;
 }
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index c8a3f63203..a5e89c528d 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -13766,14 +13766,6 @@  static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
         decode_opc_special(env, ctx);
         break;
     case OPC_SPECIAL2:
-        if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) {
-            if (MASK_SPECIAL2(ctx->opcode) == OPC_MUL) {
-                gen_arith(ctx, OPC_MUL, rd, rs, rt);
-            } else {
-                decode_ase_mxu(ctx, ctx->opcode);
-            }
-            break;
-        }
         decode_opc_special2_legacy(env, ctx);
         break;
     case OPC_SPECIAL3:
@@ -14484,6 +14476,11 @@  static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
     if (cpu_supports_isa(env, ASE_LMMI) && decode_ase_lmmi(ctx, ctx->opcode)) {
         return;
     }
+    if (TARGET_LONG_BITS == 32) {
+        if (cpu_supports_isa(env, ASE_MXU) && decode_ase_mxu(ctx, ctx->opcode)) {
+            return;
+        }
+    }
     if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
         return;
     }