From patchwork Mon Oct 31 12:33:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3531BFA3740 for ; Mon, 31 Oct 2022 12:38:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU1F-0007KG-JD; Mon, 31 Oct 2022 08:35:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opU0O-00057Q-Ku for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:35:04 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opU08-0004Qf-6i for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:35:04 -0400 Received: by mail-pg1-x535.google.com with SMTP id r18so10547687pgr.12 for ; Mon, 31 Oct 2022 05:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X6IxClWqWb6CZpSBnvYuO1So2GK7x/G/Cu2kKWY3Y/g=; b=m3p4+wzCN51/W4ls7oV3xOsRrjPaftqnO6iji8OLULaXW+zLyffD7DMS3REv8Ah/ga CukiG6bMVfh+gVP16RhaHKr6p99/DktpbbncepksWBB2Xn/54gZVZ6OIwmehe9iS3jDK ekNJ3XpXQ+0tLkJW/nyaDJTEsenYIg+LhOeooBOrAnGt3PRls/wLZOC6h0A7N3P6q8t6 1yVluRhC8cEbCfes43hWKqxAmBWH9+SacvTyRzbHliTazCvUphp8t8v9tf47o8R0c1C/ eQiJlXahUlsxYgi41aXmBefv25kKaDWGVNwXeiDW7Olq0rtOMsj7zHZTVyQ18zP5eeBQ UzZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X6IxClWqWb6CZpSBnvYuO1So2GK7x/G/Cu2kKWY3Y/g=; b=FWwKevce8Rm573z2HcU3jtMHaknQzn30rpP8UMTSAD8Vzzo9r/p4B2zzSzuMVSQzXs D8ML9MNjANDNV1nGT7nxHIqDaQeOUKUZQhde9xUhtRTUfMJYbgUaI/ES1GWffVEgPehK jCT3gyfiLcRHbcJzFXKJVRgBDLTccMlIV0COkFpkv6qgYrlFnTCzsh2iTOzuPGkrR/xV 795PWG0rzRb3YBMsLsy9a66/6vmXhVnBIdRVlfaOnubMwPExn5VzKNohCw2fFtIw9sxZ BVhwIsA4JLkF2MjzzU0F1c26Hl51ycAoRBdPRgwMCQDA7lRt7Rq8y+ipvcE858X02xdd hq2A== X-Gm-Message-State: ACrzQf0CwXQCdk5OEqLtK/uI9tC9BKNOZ0C68biLBGsR8Fnz7KET0pzm AxidH/Dnf3zaJ+gYwKC0VAZYX7p8Vjr7yTl5 X-Google-Smtp-Source: AMsMyM79Ko1XFMVf8SHXhKIVZBNR+HSEfPzS07HSzOgjvtkcBCetarQQQqOIs92u8jGElpLHMGxWWA== X-Received: by 2002:a63:5f54:0:b0:462:1149:f3b3 with SMTP id t81-20020a635f54000000b004621149f3b3mr12364519pgb.445.1667219687133; Mon, 31 Oct 2022 05:34:47 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:46 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 15/17] hw/vfio/pci: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:17 +0900 Message-Id: <20221031123319.21532-16-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::535; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org The code generating errors in pci_add_capability has a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, in pci_add_capability(), we can always assert that capabilities never overlap, and that is what happens when omitting errp. Signed-off-by: Akihiko Odaki --- hw/vfio/pci-quirks.c | 15 +++------------ hw/vfio/pci.c | 14 +++++--------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index f0147a050a..e94fd273ea 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1530,7 +1530,7 @@ const PropertyInfo qdev_prop_nv_gpudirect_clique = { static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp) { PCIDevice *pdev = &vdev->pdev; - int ret, pos = 0xC8; + int pos = 0xC8; if (vdev->nv_gpudirect_clique == 0xFF) { return 0; @@ -1547,11 +1547,7 @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp) return -EINVAL; } - ret = pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add NVIDIA GPUDirect cap: "); - return ret; - } + pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8); memset(vdev->emulated_config_bits + pos, 0xFF, 8); pos += PCI_CAP_FLAGS; @@ -1718,12 +1714,7 @@ static int vfio_add_vmd_shadow_cap(VFIOPCIDevice *vdev, Error **errp) return -EFAULT; } - ret = pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, - VMD_SHADOW_CAP_LEN, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add VMD MEMBAR Shadow cap: "); - return ret; - } + pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, VMD_SHADOW_CAP_LEN); memset(vdev->emulated_config_bits + pos, 0xFF, VMD_SHADOW_CAP_LEN); pos += PCI_CAP_FLAGS; diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index c7e3ef95a7..cad5850f5e 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1845,7 +1845,7 @@ static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); } -static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, +static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, uint8_t pos, uint8_t size, Error **errp) { uint16_t flags; @@ -1962,11 +1962,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, 1, PCI_EXP_FLAGS_VERS); } - pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, - errp); - if (pos < 0) { - return pos; - } + pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); vdev->pdev.exp.exp_cap = pos; @@ -2080,14 +2076,14 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp) case PCI_CAP_ID_PM: vfio_check_pm_reset(vdev, pos); vdev->pm_cap = pos; - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; case PCI_CAP_ID_AF: vfio_check_af_flr(vdev, pos); - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; default: - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; }