| Message ID | 20230104215835.24692-15-farosas@suse.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Allow CONFIG_TCG=n builds | expand |
On 1/4/23 13:58, Fabiano Rosas wrote: > This function is needed by common code (ptw.c), so move it along with > the other regime_* functions in internal.h. When we enable the build > without TCG, the tlb_helper.c file will not be present. Maybe better to just move to ptw.c? r~ > > Signed-off-by: Fabiano Rosas <farosas@suse.de> > --- > target/arm/internals.h | 17 ++++++++++++++--- > target/arm/tlb_helper.c | 14 -------------- > 2 files changed, 14 insertions(+), 17 deletions(-) > > diff --git a/target/arm/internals.h b/target/arm/internals.h > index 161e42d50f..3493b5cc88 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -610,9 +610,6 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, > /* Return the MMU index for a v7M CPU in the specified security state */ > ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); > > -/* Return true if the translation regime is using LPAE format page tables */ > -bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); > - > /* > * Return true if the stage 1 translation regime is using LPAE > * format page tables > @@ -777,6 +774,20 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) > return env->cp15.tcr_el[regime_el(env, mmu_idx)]; > } > > +/* Return true if the translation regime is using LPAE format page tables */ > +static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) > +{ > + int el = regime_el(env, mmu_idx); > + if (el == 2 || arm_el_is_aa64(env, el)) { > + return true; > + } > + if (arm_feature(env, ARM_FEATURE_LPAE) > + && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { > + return true; > + } > + return false; > +} > + > /** > * arm_num_brps: Return number of implemented breakpoints. > * Note that the ID register BRPS field is "number of bps - 1", > diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c > index 0f4f4fc809..31eb77f7df 100644 > --- a/target/arm/tlb_helper.c > +++ b/target/arm/tlb_helper.c > @@ -12,20 +12,6 @@ > #include "exec/helper-proto.h" > > > -/* Return true if the translation regime is using LPAE format page tables */ > -bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) > -{ > - int el = regime_el(env, mmu_idx); > - if (el == 2 || arm_el_is_aa64(env, el)) { > - return true; > - } > - if (arm_feature(env, ARM_FEATURE_LPAE) > - && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { > - return true; > - } > - return false; > -} > - > /* > * Returns true if the stage 1 translation regime is using LPAE format page > * tables. Used when raising alignment exceptions, whose FSR changes depending
diff --git a/target/arm/internals.h b/target/arm/internals.h index 161e42d50f..3493b5cc88 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -610,9 +610,6 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); -/* Return true if the translation regime is using LPAE format page tables */ -bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); - /* * Return true if the stage 1 translation regime is using LPAE * format page tables @@ -777,6 +774,20 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) return env->cp15.tcr_el[regime_el(env, mmu_idx)]; } +/* Return true if the translation regime is using LPAE format page tables */ +static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + int el = regime_el(env, mmu_idx); + if (el == 2 || arm_el_is_aa64(env, el)) { + return true; + } + if (arm_feature(env, ARM_FEATURE_LPAE) + && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { + return true; + } + return false; +} + /** * arm_num_brps: Return number of implemented breakpoints. * Note that the ID register BRPS field is "number of bps - 1", diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 0f4f4fc809..31eb77f7df 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -12,20 +12,6 @@ #include "exec/helper-proto.h" -/* Return true if the translation regime is using LPAE format page tables */ -bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - int el = regime_el(env, mmu_idx); - if (el == 2 || arm_el_is_aa64(env, el)) { - return true; - } - if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { - return true; - } - return false; -} - /* * Returns true if the stage 1 translation regime is using LPAE format page * tables. Used when raising alignment exceptions, whose FSR changes depending
This function is needed by common code (ptw.c), so move it along with the other regime_* functions in internal.h. When we enable the build without TCG, the tlb_helper.c file will not be present. Signed-off-by: Fabiano Rosas <farosas@suse.de> --- target/arm/internals.h | 17 ++++++++++++++--- target/arm/tlb_helper.c | 14 -------------- 2 files changed, 14 insertions(+), 17 deletions(-)