| Message ID | 20230127120328.2520624-2-kbastian@mail.uni-paderborn.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | TriCore instruction bugfixes | expand |
On 1/27/23 02:03, Bastian Koppelmann wrote: > we were mixing up the "c" and "d" registers. We used "d" as a > destination register und "c" as the source. According to the TriCore ISA > manual 1.6 vol 2 it is the other way round. > > Signed-off-by: Bastian Koppelmann<kbastian@mail.uni-paderborn.de> > Resolves:https://gitlab.com/qemu-project/qemu/-/issues/653 > --- > target/tricore/translate.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index df9e46c649..8de4e56b1f 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -5794,11 +5794,11 @@ static void decode_rcrw_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RCRW_IMASK: - tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f); + tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); tcg_gen_movi_tl(temp2, (1 << width) - 1); - tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp); + tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); tcg_gen_movi_tl(temp2, const4); - tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp); + tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); break; case OPC2_32_RCRW_INSERT: temp3 = tcg_temp_new();
we were mixing up the "c" and "d" registers. We used "d" as a destination register und "c" as the source. According to the TriCore ISA manual 1.6 vol 2 it is the other way round. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653 --- target/tricore/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)