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Tsirkin" , Marcel Apfelbaum , Sriram Yagnaraman Subject: [PATCH v3 3/9] igb: add ICR_RXDW Date: Tue, 31 Jan 2023 10:42:26 +0100 Message-Id: <20230131094232.28863-4-sriram.yagnaraman@est.tech> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230131094232.28863-1-sriram.yagnaraman@est.tech> References: <20230131094232.28863-1-sriram.yagnaraman@est.tech> X-ClientProxiedBy: GV3P280CA0041.SWEP280.PROD.OUTLOOK.COM (2603:10a6:150:9::19) To DBBP189MB1433.EURP189.PROD.OUTLOOK.COM (2603:10a6:10:1e7::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DBBP189MB1433:EE_|VI1P18901MB0733:EE_ X-MS-Office365-Filtering-Correlation-Id: 9d2dab2b-a9fb-4a61-971d-08db036f7cb1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ja5o6izVPJPogE5xbrNKgQWolp/exy3bF9EDmRYDF+TvK9Fzx4fMq98jOioh3uw07tPKgDT84ITqhO7/hNkeTDwgdNOFEd9N4lWKjUVnqL3pPbMHAisx5yXmIzdDLWpOmzYg2SfPqz+Ru3dHwHWnckFvzq91CdcUUeJ3BpaSXvOBsiMZnGUf9AVMAU7QgL2DXPtOeA0HROiEamFmki6C2VsALMImgcpM59fY1b3WDYui4UqDAD3DI4RfqjYlrsAWMswwvRhqFKpHh7kgqAATPSxh69+iSnbGy2HA+Jy/2MYAKOAcwa5uH2ZEVHnoob56Ro1ohUHD+Uc+OJnpqAdRUuxvwa4wTWjGF5jgba19480uRTP1kzUFKfTxY27ZG3HOw/H0ceQ038UXCE7z2Wx9X0ZPx63AbTBenhf4iWcE0vyLsyv3+myywXuR5o1vxqi0NYboLX7rwZeppdIlKaDak3jaTWVkeQU5bVK00xwJY6tRrYsBY1lThkPzpb3JWht2++NmJyjuK5Yl0Mt9cOKkaeXYdoiT5ALsHJbQsh8FkYfRdmzeSk70A7C2O6VoTiHcG6fe3lSwk3B9Oy2o3kUmmicpdJRYnom3ZbpXe7Kxo2+ZznfaqhclnGq3m+pAWZKNfghE4Cy3MpbaQfve9ZXp5zdy3p0keKSW3lwRawF2RtC986rCsWPzHgkFzRuw1TL1SR1UUxuNql1j3lEuEk3fWKlC+qPXoh/pGXvXIWI6f1I= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=sriram.yagnaraman@est.tech; helo=EUR04-HE1-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org IGB uses RXDW ICR bit to indicate that rx descriptor has been written back. This is the same as RXT0 bit in older HW. Signed-off-by: Sriram Yagnaraman --- hw/net/e1000x_regs.h | 4 ++++ hw/net/igb_core.c | 46 +++++++++++++++++--------------------------- 2 files changed, 22 insertions(+), 28 deletions(-) diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h index fb5b861135..f509db73a7 100644 --- a/hw/net/e1000x_regs.h +++ b/hw/net/e1000x_regs.h @@ -335,6 +335,7 @@ #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ #define E1000_ICR_RXO 0x00000040 /* rx overrun */ #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ +#define E1000_ICR_RXDW 0x00000080 /* rx desc written back */ #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ @@ -378,6 +379,7 @@ #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_ICS_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ @@ -407,6 +409,7 @@ #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMS_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ @@ -441,6 +444,7 @@ #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMC_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index 9c32ad5e36..e78bc3611a 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -1488,7 +1488,7 @@ igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4); uint16_t queues = 0; - uint32_t n; + uint32_t icr_bits = 0; uint8_t min_buf[ETH_ZLEN]; struct iovec min_iov; struct eth_header *ehdr; @@ -1561,6 +1561,7 @@ igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, e1000x_fcs_len(core->mac); retval = orig_size; + igb_rx_fix_l4_csum(core, core->rx_pkt); for (i = 0; i < IGB_NUM_QUEUES; i++) { if (!(queues & BIT(i))) { @@ -1569,43 +1570,32 @@ igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, igb_rx_ring_init(core, &rxr, i); - trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx); - if (!igb_has_rxbufs(core, rxr.i, total_size)) { - retval = 0; + icr_bits |= E1000_ICS_RXO; + continue; } - } - if (retval) { - n = E1000_ICR_RXT0; - - igb_rx_fix_l4_csum(core, core->rx_pkt); - - for (i = 0; i < IGB_NUM_QUEUES; i++) { - if (!(queues & BIT(i))) { - continue; - } - - igb_rx_ring_init(core, &rxr, i); + trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx); + igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); - igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); + /* Check if receive descriptor minimum threshold hit */ + if (igb_rx_descr_threshold_hit(core, rxr.i)) { + icr_bits |= E1000_ICS_RXDMT0; + } - /* Check if receive descriptor minimum threshold hit */ - if (igb_rx_descr_threshold_hit(core, rxr.i)) { - n |= E1000_ICS_RXDMT0; - } + core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx); - core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx); - } + icr_bits |= E1000_ICR_RXDW; + } - trace_e1000e_rx_written_to_guest(n); + if (icr_bits & E1000_ICR_RXDW) { + trace_e1000e_rx_written_to_guest(icr_bits); } else { - n = E1000_ICS_RXO; - trace_e1000e_rx_not_written_to_guest(n); + trace_e1000e_rx_not_written_to_guest(icr_bits); } - trace_e1000e_rx_interrupt_set(n); - igb_set_interrupt_cause(core, n); + trace_e1000e_rx_interrupt_set(icr_bits); + igb_set_interrupt_cause(core, icr_bits); return retval; }