| Message ID | 20230131133906.1956228-3-alexghiti@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Allow user to set the satp mode | expand |
Reviewed-by: Frank Chang <frank.chang@sifive.com> On Tue, Jan 31, 2023 at 10:29 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote: > This array is actually used as a boolean so swap its current char type > to a boolean and at the same time, change the type of validate_vm to > bool since it returns valid_vm_1_10_[32|64]. > > Suggested-by: Andrew Jones <ajones@ventanamicro.com> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > Reviewed-by: Bin Meng <bmeng@tinylab.org> > --- > target/riscv/csr.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 0db2c233e5..6b157806a5 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = > MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | > MIP_VSEIP; > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > -static const char valid_vm_1_10_32[16] = { > - [VM_1_10_MBARE] = 1, > - [VM_1_10_SV32] = 1 > +static const bool valid_vm_1_10_32[16] = { > + [VM_1_10_MBARE] = true, > + [VM_1_10_SV32] = true > }; > > -static const char valid_vm_1_10_64[16] = { > - [VM_1_10_MBARE] = 1, > - [VM_1_10_SV39] = 1, > - [VM_1_10_SV48] = 1, > - [VM_1_10_SV57] = 1 > +static const bool valid_vm_1_10_64[16] = { > + [VM_1_10_MBARE] = true, > + [VM_1_10_SV39] = true, > + [VM_1_10_SV48] = true, > + [VM_1_10_SV57] = true > }; > > /* Machine Information Registers */ > @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState > *env, int csrno, > return RISCV_EXCP_NONE; > } > > -static int validate_vm(CPURISCVState *env, target_ulong vm) > +static bool validate_vm(CPURISCVState *env, target_ulong vm) > { > if (riscv_cpu_mxl(env) == MXL_RV32) { > return valid_vm_1_10_32[vm & 0xf]; > @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, > int csrno, > static RISCVException write_satp(CPURISCVState *env, int csrno, > target_ulong val) > { > - target_ulong vm, mask; > + target_ulong mask; > + bool vm; > > if (!riscv_feature(env, RISCV_FEATURE_MMU)) { > return RISCV_EXCP_NONE; > -- > 2.37.2 > > >
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0db2c233e5..6b157806a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const char valid_vm_1_10_32[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV32] = 1 +static const bool valid_vm_1_10_32[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV32] = true }; -static const char valid_vm_1_10_64[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV39] = 1, - [VM_1_10_SV48] = 1, - [VM_1_10_SV57] = 1 +static const bool valid_vm_1_10_64[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV39] = true, + [VM_1_10_SV48] = true, + [VM_1_10_SV57] = true }; /* Machine Information Registers */ @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int validate_vm(CPURISCVState *env, target_ulong vm) +static bool validate_vm(CPURISCVState *env, target_ulong vm) { if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno, static RISCVException write_satp(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong vm, mask; + target_ulong mask; + bool vm; if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return RISCV_EXCP_NONE;