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[5.69.146.176]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b003da28dfdedcsm6312144wmq.5.2023.02.10.08.39.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 08:39:38 -0800 (PST) From: Jean-Philippe Brucker To: eric.auger@redhat.com Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, ola.hugosson@arm.com, Jean-Philippe Brucker Subject: [PATCH 1/2] hw/arm/smmu-common: Support 64-bit addresses Date: Fri, 10 Feb 2023 16:37:31 +0000 Message-Id: <20230210163731.970130-2-jean-philippe@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230210163731.970130-1-jean-philippe@linaro.org> References: <20230210163731.970130-1-jean-philippe@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=jean-philippe@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Addresses targeting the second translation table (TTB1) in the SMMU have all upper bits set. Ensure the IOMMU region covers all 64 bits. Signed-off-by: Jean-Philippe Brucker Reviewed-by: Richard Henderson --- hw/arm/smmu-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 733c964778..2b8c67b9a1 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -439,7 +439,7 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), s->mrtypename, - OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS); + OBJECT(s), name, UINT64_MAX); address_space_init(&sdev->as, MEMORY_REGION(&sdev->iommu), name); trace_smmu_add_mr(name);