| Message ID | 20230217161027.56859-1-ivan.klokov@syntacore.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | disas/riscv Fix ctzw disassemble | expand |
On 2/17/23 13:10, Ivan Klokov wrote: > Due to typo in opcode list, ctzw is disassembled as clzw instruction. > > Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions") > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > v2: > - added fixes line > --- > disas/riscv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index ddda687c13..54455aaaa8 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -1645,7 +1645,7 @@ const rv_opcode_data opcode_data[] = { > { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > + { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, > { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
On 2023/2/18 00:10, Ivan Klokov wrote: > Due to typo in opcode list, ctzw is disassembled as clzw instruction. > > Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions") > Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> > --- > v2: > - added fixes line Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Weiwei Li > --- > disas/riscv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index ddda687c13..54455aaaa8 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -1645,7 +1645,7 @@ const rv_opcode_data opcode_data[] = { > { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, > { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > - { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > + { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, > { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
diff --git a/disas/riscv.c b/disas/riscv.c index ddda687c13..54455aaaa8 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1645,7 +1645,7 @@ const rv_opcode_data opcode_data[] = { { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, - { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
Due to typo in opcode list, ctzw is disassembled as clzw instruction. Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions") Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> --- v2: - added fixes line --- disas/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)