Message ID | 20230224185908.32706-7-palmer@rivosinc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [PULL,1/8] hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() | expand |
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index d1126a6066..4bc4113531 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -441,9 +441,12 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, } } - if ((privs & *allowed_privs) == privs) { - ret = i; - } + /* + * If matching address range was found, the protection bits + * defined with PMP must be used. We shouldn't fallback on + * finding default privileges. + */ + ret = i; break; } }