| Message ID | 20230322092704.22776-3-sriram.yagnaraman@est.tech (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | igb: merge changes from <20221229190817.25500-1-sriram.yagnaraman@est.tech> | expand |
On 22/3/23 10:26, Sriram Yagnaraman wrote: > Use PFRSTD to reset RSTI bit for VFs, and raise VFLRE interrupt when VF > is reset. > > Signed-off-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech> > --- > hw/net/igb_core.c | 33 +++++++++++++++++++++------------ > hw/net/igb_regs.h | 3 +++ > hw/net/trace-events | 2 ++ > 3 files changed, 26 insertions(+), 12 deletions(-) > > diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c > index 596039aab8..fe6c7518e9 100644 > --- a/hw/net/igb_core.c > +++ b/hw/net/igb_core.c > @@ -1895,14 +1895,6 @@ static void igb_set_eims(IGBCore *core, int index, uint32_t val) > igb_update_interrupt_state(core); > } > > -static void igb_vf_reset(IGBCore *core, uint16_t vfn) > -{ > - /* TODO: Reset of the queue enable and the interrupt registers of the VF. */ > - > - core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; > - core->mac[V2PMAILBOX0 + vfn] = E1000_V2PMAILBOX_RSTD; > -} > - > static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn) > { > uint32_t ent = core->mac[VTIVAR_MISC + vfn]; > @@ -1980,6 +1972,17 @@ static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val) > } > } > > +static void igb_vf_reset(IGBCore *core, uint16_t vfn) > +{ > + /* disable Rx and Tx for the VF*/ > + core->mac[VFTE] &= ~BIT(vfn); > + core->mac[VFRE] &= ~BIT(vfn); > + /* indicate VF reset to PF */ > + core->mac[VFLRE] |= BIT(vfn); > + /* VFLRE and mailbox use the same interrupt cause */ > + mailbox_interrupt_to_pf(core); > +} Orthogonal to this patch, I'm surprised to see a function named igb_vf_reset() which is not called by igb_reset().
> -----Original Message----- > From: Philippe Mathieu-Daudé <philmd@linaro.org> > Sent: Wednesday, 22 March 2023 11:29 > To: Sriram Yagnaraman <sriram.yagnaraman@est.tech> > Cc: qemu-devel@nongnu.org; Akihiko Odaki <akihiko.odaki@daynix.com>; > Jason Wang <jasowang@redhat.com>; Dmitry Fleytman > <dmitry.fleytman@gmail.com>; Michael S . Tsirkin <mst@redhat.com>; Marcel > Apfelbaum <marcel.apfelbaum@gmail.com> > Subject: Re: [PATCH v8 2/8] igb: handle PF/VF reset properly > > On 22/3/23 10:26, Sriram Yagnaraman wrote: > > Use PFRSTD to reset RSTI bit for VFs, and raise VFLRE interrupt when > > VF is reset. > > > > Signed-off-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech> > > --- > > hw/net/igb_core.c | 33 +++++++++++++++++++++------------ > > hw/net/igb_regs.h | 3 +++ > > hw/net/trace-events | 2 ++ > > 3 files changed, 26 insertions(+), 12 deletions(-) > > > > diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index > > 596039aab8..fe6c7518e9 100644 > > --- a/hw/net/igb_core.c > > +++ b/hw/net/igb_core.c > > @@ -1895,14 +1895,6 @@ static void igb_set_eims(IGBCore *core, int > index, uint32_t val) > > igb_update_interrupt_state(core); > > } > > > > -static void igb_vf_reset(IGBCore *core, uint16_t vfn) -{ > > - /* TODO: Reset of the queue enable and the interrupt registers of the VF. > */ > > - > > - core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; > > - core->mac[V2PMAILBOX0 + vfn] = E1000_V2PMAILBOX_RSTD; > > -} > > - > > static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn) > > { > > uint32_t ent = core->mac[VTIVAR_MISC + vfn]; @@ -1980,6 +1972,17 > > @@ static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val) > > } > > } > > > > +static void igb_vf_reset(IGBCore *core, uint16_t vfn) { > > + /* disable Rx and Tx for the VF*/ > > + core->mac[VFTE] &= ~BIT(vfn); > > + core->mac[VFRE] &= ~BIT(vfn); > > + /* indicate VF reset to PF */ > > + core->mac[VFLRE] |= BIT(vfn); > > + /* VFLRE and mailbox use the same interrupt cause */ > > + mailbox_interrupt_to_pf(core); > > +} > > Orthogonal to this patch, I'm surprised to see a function named > igb_vf_reset() which is not called by igb_reset(). Thanks for the pertinent comment, will fix it. On PF reset, the hardware will assert RSTI bit on all VF mailboxes, which should in turn trigger a VF reset after the PF reset is complete.
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index 596039aab8..fe6c7518e9 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -1895,14 +1895,6 @@ static void igb_set_eims(IGBCore *core, int index, uint32_t val) igb_update_interrupt_state(core); } -static void igb_vf_reset(IGBCore *core, uint16_t vfn) -{ - /* TODO: Reset of the queue enable and the interrupt registers of the VF. */ - - core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; - core->mac[V2PMAILBOX0 + vfn] = E1000_V2PMAILBOX_RSTD; -} - static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn) { uint32_t ent = core->mac[VTIVAR_MISC + vfn]; @@ -1980,6 +1972,17 @@ static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val) } } +static void igb_vf_reset(IGBCore *core, uint16_t vfn) +{ + /* disable Rx and Tx for the VF*/ + core->mac[VFTE] &= ~BIT(vfn); + core->mac[VFRE] &= ~BIT(vfn); + /* indicate VF reset to PF */ + core->mac[VFLRE] |= BIT(vfn); + /* VFLRE and mailbox use the same interrupt cause */ + mailbox_interrupt_to_pf(core); +} + static void igb_w1c(IGBCore *core, int index, uint32_t val) { core->mac[index] &= ~val; @@ -2234,14 +2237,20 @@ igb_set_status(IGBCore *core, int index, uint32_t val) static void igb_set_ctrlext(IGBCore *core, int index, uint32_t val) { - trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), - !!(val & E1000_CTRL_EXT_SPD_BYPS)); - - /* TODO: PFRSTD */ + trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), + !!(val & E1000_CTRL_EXT_SPD_BYPS), + !!(val & E1000_CTRL_EXT_PFRSTD)); /* Zero self-clearing bits */ val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); core->mac[CTRL_EXT] = val; + + if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) { + for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { + core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; + core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD; + } + } } static void diff --git a/hw/net/igb_regs.h b/hw/net/igb_regs.h index 00934d4f20..a658f9b53f 100644 --- a/hw/net/igb_regs.h +++ b/hw/net/igb_regs.h @@ -240,6 +240,9 @@ union e1000_adv_rx_desc { /* from igb/e1000_defines.h */ +/* Physical Func Reset Done Indication */ +#define E1000_CTRL_EXT_PFRSTD 0x00004000 + #define E1000_IVAR_VALID 0x80 #define E1000_GPIE_NSICR 0x00000001 #define E1000_GPIE_MSIX_MODE 0x00000010 diff --git a/hw/net/trace-events b/hw/net/trace-events index 65753411fc..d35554fce8 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -280,6 +280,8 @@ igb_core_mdic_read_unhandled(uint32_t addr) "MDIC READ: PHY[%u] UNHANDLED" igb_core_mdic_write(uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u] = 0x%x" igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] UNHANDLED" +igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfrstd) "Set extended link params: ASD check: %d, Speed select bypass: %d, PF reset done: %d" + igb_rx_desc_buff_size(uint32_t b) "buffer size: %u" igb_rx_desc_buff_write(uint64_t addr, uint16_t offset, const void* source, uint32_t len) "addr: 0x%"PRIx64", offset: %u, from: %p, length: %u"
Use PFRSTD to reset RSTI bit for VFs, and raise VFLRE interrupt when VF is reset. Signed-off-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech> --- hw/net/igb_core.c | 33 +++++++++++++++++++++------------ hw/net/igb_regs.h | 3 +++ hw/net/trace-events | 2 ++ 3 files changed, 26 insertions(+), 12 deletions(-)