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Tsirkin" , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Sriram Yagnaraman Subject: [PATCH v9 2/8] igb: handle PF/VF reset properly Date: Wed, 22 Mar 2023 14:04:34 +0100 Message-Id: <20230322130440.26808-3-sriram.yagnaraman@est.tech> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230322130440.26808-1-sriram.yagnaraman@est.tech> References: <20230322130440.26808-1-sriram.yagnaraman@est.tech> X-ClientProxiedBy: GV3P280CA0001.SWEP280.PROD.OUTLOOK.COM (2603:10a6:150:b::31) To DBBP189MB1433.EURP189.PROD.OUTLOOK.COM (2603:10a6:10:1e7::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DBBP189MB1433:EE_|AS1P189MB1936:EE_ X-MS-Office365-Filtering-Correlation-Id: a40debcf-f6a2-4d92-8eb0-08db2ade0cf4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S63mII6/TjQOs8rBAD4+fQRO+GD8SqWK8OBtBdr/j/v6KayOutyViypLuuiFs2/61qOc93zi0urPm3Gvt0g6nZrgun+OQNc8phzhr2xLanyDKmHF1XZwJ8RQqs7xT6ot9J5eOWxMexZlN81s8gTp7YTETlPXjcX1mlbEUdZCboZc3MlkeTSQD1B0xw9sdu3XCuC/6Hb310E5/WsvZHE14g5XpaBuwCZaQLsqegtIyTZBssbXHghw9TkgjKdAGkS3I/LHg+JEakq64/eDGEZNNyfKWzh7MQZBMFJoC4tjksl6BLZIfpK+3OQ/dihOUvHxztsJjwwH11IGGShrnjfxv82/pU2xdtgIXsQ3gvpy8+MTHgRZCWtHUVhyVO1vnngByOPnKQ8bX88+bJdQcLZBVcJBBqPbARcD2t2IeS+wMMEGy9Y+ePEQO9wBA7rJ2Cxt8sgvXHbETdHktRq7fzSklRsgxXTEWJU8PlGCrOxHpxWtTAUCZxnW97DCkxlr1nHB/MzkRC6qjkeSxJpcHl0zNu1w6PcicdArhis7DGWC3VoehCEzrwp0VbNB2pUMtsgssLqYhIcf10+FxB5si3vPEtekTqZ9v0bCt9iCkPJpV/p8oLqB7ImJjanaTIOibrASuAFQUNEHQMjhR+q6MFoROWI20y3G4BAR+XymPKmHPjlRT7wvPxASQnQ70pEIER0eQNmUn1RYNTu1bxynu31dDAiW3IpAEJ01dCpXVt4JzXs= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=sriram.yagnaraman@est.tech; helo=EUR04-HE1-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use PFRSTD to reset RSTI bit for VFs, and raise VFLRE interrupt when VF is reset. Signed-off-by: Sriram Yagnaraman --- hw/net/igb_core.c | 38 ++++++++++++++++++++++++++------------ hw/net/igb_regs.h | 3 +++ hw/net/trace-events | 2 ++ 3 files changed, 31 insertions(+), 12 deletions(-) diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index 596039aab8..0fde8ef854 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -1895,14 +1895,6 @@ static void igb_set_eims(IGBCore *core, int index, uint32_t val) igb_update_interrupt_state(core); } -static void igb_vf_reset(IGBCore *core, uint16_t vfn) -{ - /* TODO: Reset of the queue enable and the interrupt registers of the VF. */ - - core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; - core->mac[V2PMAILBOX0 + vfn] = E1000_V2PMAILBOX_RSTD; -} - static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn) { uint32_t ent = core->mac[VTIVAR_MISC + vfn]; @@ -1980,6 +1972,17 @@ static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val) } } +static void igb_vf_reset(IGBCore *core, uint16_t vfn) +{ + /* disable Rx and Tx for the VF*/ + core->mac[VFTE] &= ~BIT(vfn); + core->mac[VFRE] &= ~BIT(vfn); + /* indicate VF reset to PF */ + core->mac[VFLRE] |= BIT(vfn); + /* VFLRE and mailbox use the same interrupt cause */ + mailbox_interrupt_to_pf(core); +} + static void igb_w1c(IGBCore *core, int index, uint32_t val) { core->mac[index] &= ~val; @@ -2234,14 +2237,20 @@ igb_set_status(IGBCore *core, int index, uint32_t val) static void igb_set_ctrlext(IGBCore *core, int index, uint32_t val) { - trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), - !!(val & E1000_CTRL_EXT_SPD_BYPS)); - - /* TODO: PFRSTD */ + trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), + !!(val & E1000_CTRL_EXT_SPD_BYPS), + !!(val & E1000_CTRL_EXT_PFRSTD)); /* Zero self-clearing bits */ val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); core->mac[CTRL_EXT] = val; + + if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) { + for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { + core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; + core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD; + } + } } static void @@ -4024,6 +4033,11 @@ static void igb_reset(IGBCore *core, bool sw) e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); + for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { + /* Set RSTI, so VF can identify a PF reset is in progress */ + core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI; + } + for (i = 0; i < ARRAY_SIZE(core->tx); i++) { tx = &core->tx[i]; net_tx_pkt_reset(tx->tx_pkt); diff --git a/hw/net/igb_regs.h b/hw/net/igb_regs.h index 00934d4f20..a658f9b53f 100644 --- a/hw/net/igb_regs.h +++ b/hw/net/igb_regs.h @@ -240,6 +240,9 @@ union e1000_adv_rx_desc { /* from igb/e1000_defines.h */ +/* Physical Func Reset Done Indication */ +#define E1000_CTRL_EXT_PFRSTD 0x00004000 + #define E1000_IVAR_VALID 0x80 #define E1000_GPIE_NSICR 0x00000001 #define E1000_GPIE_MSIX_MODE 0x00000010 diff --git a/hw/net/trace-events b/hw/net/trace-events index 65753411fc..d35554fce8 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -280,6 +280,8 @@ igb_core_mdic_read_unhandled(uint32_t addr) "MDIC READ: PHY[%u] UNHANDLED" igb_core_mdic_write(uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u] = 0x%x" igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] UNHANDLED" +igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfrstd) "Set extended link params: ASD check: %d, Speed select bypass: %d, PF reset done: %d" + igb_rx_desc_buff_size(uint32_t b) "buffer size: %u" igb_rx_desc_buff_write(uint64_t addr, uint16_t offset, const void* source, uint32_t len) "addr: 0x%"PRIx64", offset: %u, from: %p, length: %u"