[v4,7/7] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write

Commit Message

Weiwei Li April 22, 2023, 1:03 p.m. UTC

Use pmp_update_rule_addr() and pmp_update_rule_nums() separately to
update rule nums only once for each pmpcfg_csr_write. Then we can also
move tlb_flush into pmp_update_rule_nums().

Signed-off-by: Weiwei Li <[e-mail]>
Signed-off-by: Junqiang Wang <[e-mail]>
---
 target/riscv/pmp.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Patch

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index b0f1b0a715..5b765a9807 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -121,7 +121,7 @@  static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
             qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
         } else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) {
             env->pmp_state.pmp[pmp_index].cfg_reg = val;
-            pmp_update_rule(env, pmp_index);
+            pmp_update_rule_addr(env, pmp_index);
             return true;
         }
     } else {
@@ -207,6 +207,8 @@  void pmp_update_rule_nums(CPURISCVState *env)
             env->pmp_state.num_rules++;
         }
     }
+
+    tlb_flush(env_cpu(env));
 }
 
 /*
@@ -492,7 +494,7 @@  void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
 
     /* If PMP permission of any addr has been changed, flush TLB pages. */
     if (modified) {
-        tlb_flush(env_cpu(env));
+        pmp_update_rule_nums(env);
     }
 }
 
@@ -545,7 +547,6 @@  void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
             if (env->pmp_state.pmp[addr_index].addr_reg != val) {
                 env->pmp_state.pmp[addr_index].addr_reg = val;
                 pmp_update_rule(env, addr_index);
-                tlb_flush(env_cpu(env));
             }
         } else {
             qemu_log_mask(LOG_GUEST_ERROR,