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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:28 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 38/89] target/riscv: remove cpu->cfg.ext_c Date: Fri, 5 May 2023 11:01:50 +1000 Message-Id: <20230505010241.21812-39-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza Create a new "c" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are replaced with riscv_has_ext(env, RVC). Remove the old "c" property and 'ext_c' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 9 ++++----- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1d1a17d85b..9a3847329c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -428,7 +428,6 @@ struct RISCVCPUConfig { bool ext_m; bool ext_f; bool ext_d; - bool ext_c; bool ext_s; bool ext_u; bool ext_h; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3770fd4f6f..2e00b8f20a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -407,7 +407,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.ext_g = true; - cpu->cfg.ext_c = true; cpu->cfg.ext_u = true; cpu->cfg.ext_s = true; cpu->cfg.ext_icsr = true; @@ -957,7 +956,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } - if (cpu->cfg.ext_c) { + if (riscv_has_ext(env, RVC)) { cpu->cfg.ext_zca = true; if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { cpu->cfg.ext_zcf = true; @@ -1168,7 +1167,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) if (riscv_cpu_cfg(env)->ext_d) { ext |= RVD; } - if (riscv_cpu_cfg(env)->ext_c) { + if (riscv_has_ext(env, RVC)) { ext |= RVC; } if (riscv_cpu_cfg(env)->ext_s) { @@ -1498,6 +1497,8 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { {.name = "a", .description = "Atomic instructions", .misa_bit = RVA, .enabled = true}, + {.name = "c", .description = "Compressed instructions", + .misa_bit = RVC, .enabled = true}, }; static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1526,7 +1527,6 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), - DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1649,7 +1649,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_f = misa_ext & RVF; cpu->cfg.ext_d = misa_ext & RVD; cpu->cfg.ext_v = misa_ext & RVV; - cpu->cfg.ext_c = misa_ext & RVC; cpu->cfg.ext_s = misa_ext & RVS; cpu->cfg.ext_u = misa_ext & RVU; cpu->cfg.ext_h = misa_ext & RVH;