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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:44 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 43/89] target/riscv: remove cpu->cfg.ext_m Date: Fri, 5 May 2023 11:01:55 +1000 Message-Id: <20230505010241.21812-44-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=alistair23@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza Create a new "m" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are replaced with riscv_has_ext(env, RVM). Remove the old "m" property and 'ext_m' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-12-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 10 +++++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2b42de60b1..71540a33ec 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { struct RISCVCPUConfig { bool ext_g; - bool ext_m; bool ext_s; bool ext_u; bool ext_h; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 33db4fa4b2..24640450c7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -817,13 +817,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) CPURISCVState *env = &cpu->env; /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && + riscv_has_ext(env, RVM) && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_m = true; cpu->cfg.ext_icsr = true; cpu->cfg.ext_ifencei = true; @@ -1153,7 +1153,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) if (riscv_has_ext(env, RVE)) { ext |= RVE; } - if (riscv_cpu_cfg(env)->ext_m) { + if (riscv_has_ext(env, RVM)) { ext |= RVM; } if (riscv_has_ext(env, RVA)) { @@ -1505,6 +1505,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { .misa_bit = RVI, .enabled = true}, {.name = "e", .description = "Base integer instruction set (embedded)", .misa_bit = RVE, .enabled = false}, + {.name = "m", .description = "Integer multiplication and division", + .misa_bit = RVM, .enabled = true}, }; static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1528,7 +1530,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext != 0) { - cpu->cfg.ext_m = misa_ext & RVM; cpu->cfg.ext_v = misa_ext & RVV; cpu->cfg.ext_s = misa_ext & RVS; cpu->cfg.ext_u = misa_ext & RVU;