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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:58 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 47/89] target/riscv: remove cpu->cfg.ext_j Date: Fri, 5 May 2023 11:01:59 +1000 Message-Id: <20230505010241.21812-48-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza Create a new "j" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are replaced with riscv_has_ext(env, RVJ). Remove the old "j" property and 'ext_j' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 6 +++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 823be82239..1aff93ba91 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { struct RISCVCPUConfig { bool ext_g; - bool ext_j; bool ext_v; bool ext_zba; bool ext_zbb; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6291224905..3bdd6875a8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1178,7 +1178,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) if (riscv_cpu_cfg(env)->ext_v) { ext |= RVV; } - if (riscv_cpu_cfg(env)->ext_j) { + if (riscv_has_ext(env, RVJ)) { ext |= RVJ; } @@ -1511,6 +1511,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { .misa_bit = RVU, .enabled = true}, {.name = "h", .description = "Hypervisor", .misa_bit = RVH, .enabled = true}, + {.name = "x-j", .description = "Dynamic translated languages", + .misa_bit = RVJ, .enabled = false}, }; static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1607,7 +1609,6 @@ static Property riscv_cpu_extensions[] = { /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), - DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), @@ -1648,7 +1649,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext != 0) { cpu->cfg.ext_v = misa_ext & RVV; - cpu->cfg.ext_j = misa_ext & RVJ; /* * We don't want to set the default riscv_cpu_extensions