[PULL,50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()

Commit Message

Alistair Francis May 5, 2023, 1:02 a.m. UTC

From: Daniel Henrique Barboza <[e-mail]>

This CPU is enabling G via cfg.ext_g and, at the same time, setting
IMAFD in set_misa() and cfg.ext_icsr.

riscv_cpu_validate_set_extensions() is already doing that, so there's no
need for cpu_init() setups to worry about setting G and its extensions.

Signed-off-by: Daniel Henrique Barboza <[e-mail]>
Reviewed-by: Weiwei Li <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
Message-Id: <[e-mail]>
Signed-off-by: Alistair Francis <[e-mail]>
---
 target/riscv/cpu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1ecb82bb5d..b005bcb786 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -403,11 +403,10 @@  static void rv64_thead_c906_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_misa(env, MXL_RV64, RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_11_0);
 
     cpu->cfg.ext_g = true;
-    cpu->cfg.ext_icsr = true;
     cpu->cfg.ext_zfh = true;
     cpu->cfg.mmu = true;
     cpu->cfg.ext_xtheadba = true;