diff mbox series

[v3,8/9] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts

Message ID 20230515092655.171206-9-npiggin@gmail.com (mailing list archive)
State New, archived
Headers show
Series target/ppc: Assorted ppc target fixes | expand

Commit Message

Nicholas Piggin May 15, 2023, 9:26 a.m. UTC 
System call interrupts in ISA v3.1 CPUs add a LEV indication in SRR1
that corresponds with the LEV field of the instruction that caused the
interrupt.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v2: new patch.

 target/ppc/excp_helper.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 529a4513a3..25f9fa9d3f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1559,6 +1559,10 @@  static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
             vhc->hypercall(cpu->vhyp, cpu);
             return;
         }
+        if (env->insns_flags2 & PPC2_ISA310) {
+            /* ISAv3.1 puts LEV into SRR1 */
+            msr |= lev << 20;
+        }
         if (lev == 1) {
             new_msr |= (target_ulong)MSR_HVB;
         }