[v6,09/12] target/riscv: Flush TLB when pmpaddr is updated

Commit Message

Weiwei Li May 17, 2023, 9:15 a.m. UTC

TLB should be flushed not only for pmpcfg csr changes, but also for
pmpaddr csr changes.

Signed-off-by: Weiwei Li <[e-mail]>
Signed-off-by: Junqiang Wang <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
Reviewed-by: LIU Zhiwei <[e-mail]>
---
 target/riscv/pmp.c | 1 +
 1 file changed, 1 insertion(+)

Patch

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index efe72afe29..70fb2327f7 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -531,6 +531,7 @@  void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
             if (is_next_cfg_tor) {
                 pmp_update_rule_addr(env, addr_index + 1);
             }
+            tlb_flush(env_cpu(env));
         } else {
             qemu_log_mask(LOG_GUEST_ERROR,
                           "ignoring pmpaddr write - locked\n");