[v6,07/12] target/riscv: Flush TLB when MMWP or MML bits are changed

Commit Message

Weiwei Li May 17, 2023, 9:15 a.m. UTC

MMWP and MML bits may affect the allowed privs of PMP entries and the
default privs, both of which may change the allowed privs of exsited
TLB entries. So we need flush TLB when they are changed.

Signed-off-by: Weiwei Li <[e-mail]>
Signed-off-by: Junqiang Wang <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
---
 target/riscv/pmp.c | 3 +++
 1 file changed, 3 insertions(+)

Patch

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 666fbb74b9..8cb8519b0c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -578,6 +578,9 @@  void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
     if (riscv_cpu_cfg(env)->epmp) {
         /* Sticky bits */
         val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+        if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
+            tlb_flush(env_cpu(env));
+        }
     } else {
         val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
     }