| Message ID | 20230521102307.87081-3-jiaxun.yang@flygoat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/mips/loongson3_virt: Wire up loongarch_ipi device | expand |
Hi, 在 2023/5/21 下午6:23, Jiaxun Yang 写道: > IOCSR based send features are tied to LoongArch's CPU implmentation, > ifdef them for LoongArch only so we can build loongarch_ipi on MIPS. > > Note that Loongson-3A4000 have IOCSR as well, so we may implement > those features for MIPS in future. > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > hw/intc/loongarch_ipi.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c > index 3e453816524e..895a2ee96e1e 100644 > --- a/hw/intc/loongarch_ipi.c > +++ b/hw/intc/loongarch_ipi.c > @@ -50,6 +50,7 @@ static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size) > return ret; > } > > +#ifdef TARGET_LOONGARCH64 How about adding one or three properties to LoongArchIPI? and set these properties when starting the device. This patch conflicts with patch [1], will it affect your patch? [1]: https://patchew.org/QEMU/20230518014115.117869-1-gaosong@loongson.cn/20230518014115.117869-3-gaosong@loongson.cn/ Thanks. Song Gao > static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr) > { > int i, mask = 0, data = 0; > @@ -140,6 +141,25 @@ static void any_send(uint64_t val) > env = &cpu->env; > send_ipi_data(env, val, addr); > } > +#else > +static void ipi_send(uint64_t val) > +{ > + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n", > + __func__, val); > +} > + > +static void mail_send(uint64_t val) > +{ > + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n", > + __func__, val); > +} > + > +static void any_send(uint64_t val) > +{ > + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n", > + __func__, val); > +} > +#endif > > static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val, > unsigned size)
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 3e453816524e..895a2ee96e1e 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -50,6 +50,7 @@ static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size) return ret; } +#ifdef TARGET_LOONGARCH64 static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr) { int i, mask = 0, data = 0; @@ -140,6 +141,25 @@ static void any_send(uint64_t val) env = &cpu->env; send_ipi_data(env, val, addr); } +#else +static void ipi_send(uint64_t val) +{ + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n", + __func__, val); +} + +static void mail_send(uint64_t val) +{ + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n", + __func__, val); +} + +static void any_send(uint64_t val) +{ + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented send 0x%" PRIx64 "\n", + __func__, val); +} +#endif static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size)
IOCSR based send features are tied to LoongArch's CPU implmentation, ifdef them for LoongArch only so we can build loongarch_ipi on MIPS. Note that Loongson-3A4000 have IOCSR as well, so we may implement those features for MIPS in future. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- hw/intc/loongarch_ipi.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)