| Message ID | 20230603233612.125879-4-npiggin@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ppc/pnv: Add chiptod and core timebase state machine models | expand |
On 6/4/23 01:36, Nicholas Piggin wrote: > TFMR is the Time Facility Management Register which is specific to POWER > CPUs, and used for the purpose of timebase management (generally by > firmware, not the OS). > > This adds an initial simple TFMR register, which will form part of the > core timebase facility model in the next patch. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > target/ppc/cpu_init.c | 2 +- > target/ppc/helper.h | 2 ++ > target/ppc/spr_common.h | 2 ++ > target/ppc/timebase_helper.c | 13 +++++++++++++ > target/ppc/translate.c | 10 ++++++++++ > 5 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index da0f7a7159..37088021d2 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -5662,7 +5662,7 @@ static void register_power_common_book4_sprs(CPUPPCState *env) > spr_register_hv(env, SPR_TFMR, "TFMR", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > + &spr_read_tfmr, &spr_write_tfmr, > 0x00000000); > spr_register_hv(env, SPR_LDBAR, "LDBAR", > SPR_NOACCESS, SPR_NOACCESS, > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index 16bb485c1a..166cacb3f9 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -746,6 +746,8 @@ DEF_HELPER_2(store_40x_dbcr0, void, env, tl) > DEF_HELPER_2(store_40x_sler, void, env, tl) > DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl) > DEF_HELPER_FLAGS_2(store_booke_tsr, TCG_CALL_NO_RWG, void, env, tl) > +DEF_HELPER_1(load_tfmr, tl, env) > +DEF_HELPER_2(store_tfmr, void, env, tl) > DEF_HELPER_3(store_ibatl, void, env, i32, tl) > DEF_HELPER_3(store_ibatu, void, env, i32, tl) > DEF_HELPER_3(store_dbatl, void, env, i32, tl) > diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h > index d6c679cd99..8ab17123a4 100644 > --- a/target/ppc/spr_common.h > +++ b/target/ppc/spr_common.h > @@ -196,6 +196,8 @@ void spr_write_ebb(DisasContext *ctx, int sprn, int gprn); > void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn); > void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn); > void spr_write_hmer(DisasContext *ctx, int sprn, int gprn); > +void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn); > +void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn); > void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); > void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn); > #endif > diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c > index de1ee85e0b..34b1d5ad05 100644 > --- a/target/ppc/timebase_helper.c > +++ b/target/ppc/timebase_helper.c > @@ -270,6 +270,19 @@ void helper_store_booke_tsr(CPUPPCState *env, target_ulong val) > store_booke_tsr(env, val); > } > > +#if defined(TARGET_PPC64) > +/* POWER processor Timebase Facility */ > +target_ulong helper_load_tfmr(CPUPPCState *env) > +{ > + return env->spr[SPR_TFMR]; > +} > + > +void helper_store_tfmr(CPUPPCState *env, target_ulong val) > +{ > + env->spr[SPR_TFMR] = val; > +} > +#endif > + > /*****************************************************************************/ > /* Embedded PowerPC specific helpers */ > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 8b312b46e0..9dcd66eac8 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -1255,6 +1255,16 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) > spr_store_dump_spr(sprn); > } > > +void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) > +{ > + gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); > +} > + > +void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) > +{ > + gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); > +} > + > void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) > { > gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index da0f7a7159..37088021d2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5662,7 +5662,7 @@ static void register_power_common_book4_sprs(CPUPPCState *env) spr_register_hv(env, SPR_TFMR, "TFMR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_tfmr, &spr_write_tfmr, 0x00000000); spr_register_hv(env, SPR_LDBAR, "LDBAR", SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 16bb485c1a..166cacb3f9 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -746,6 +746,8 @@ DEF_HELPER_2(store_40x_dbcr0, void, env, tl) DEF_HELPER_2(store_40x_sler, void, env, tl) DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_booke_tsr, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_1(load_tfmr, tl, env) +DEF_HELPER_2(store_tfmr, void, env, tl) DEF_HELPER_3(store_ibatl, void, env, i32, tl) DEF_HELPER_3(store_ibatu, void, env, i32, tl) DEF_HELPER_3(store_dbatl, void, env, i32, tl) diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index d6c679cd99..8ab17123a4 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -196,6 +196,8 @@ void spr_write_ebb(DisasContext *ctx, int sprn, int gprn); void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn); void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn); void spr_write_hmer(DisasContext *ctx, int sprn, int gprn); +void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn); +void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn); void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn); #endif diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index de1ee85e0b..34b1d5ad05 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -270,6 +270,19 @@ void helper_store_booke_tsr(CPUPPCState *env, target_ulong val) store_booke_tsr(env, val); } +#if defined(TARGET_PPC64) +/* POWER processor Timebase Facility */ +target_ulong helper_load_tfmr(CPUPPCState *env) +{ + return env->spr[SPR_TFMR]; +} + +void helper_store_tfmr(CPUPPCState *env, target_ulong val) +{ + env->spr[SPR_TFMR] = val; +} +#endif + /*****************************************************************************/ /* Embedded PowerPC specific helpers */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 8b312b46e0..9dcd66eac8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1255,6 +1255,16 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) spr_store_dump_spr(sprn); } +void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); +} + +void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); +} + void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) { gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
TFMR is the Time Facility Management Register which is specific to POWER CPUs, and used for the purpose of timebase management (generally by firmware, not the OS). This adds an initial simple TFMR register, which will form part of the core timebase facility model in the next patch. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- target/ppc/cpu_init.c | 2 +- target/ppc/helper.h | 2 ++ target/ppc/spr_common.h | 2 ++ target/ppc/timebase_helper.c | 13 +++++++++++++ target/ppc/translate.c | 10 ++++++++++ 5 files changed, 28 insertions(+), 1 deletion(-)