diff mbox series

[v2,8/8] target/tricore: Fix ICR.IE offset in RESTORE insn

Message ID 20230616152808.1499082-9-kbastian@mail.uni-paderborn.de (mailing list archive)
State New, archived
Headers show
Series TriCore Privilege Levels | expand

Commit Message

Bastian Koppelmann June 16, 2023, 3:28 p.m. UTC 
from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target/tricore/translate.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 5f9bc2b558..eb06df2323 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -7957,7 +7957,8 @@  static void decode_sys_interrupts(DisasContext *ctx)
     case OPC2_32_SYS_RESTORE:
         if (has_feature(ctx, TRICORE_FEATURE_16)) {
             if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
-                tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
+                tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1],
+                        ctx->icr_ie_offset, 1);
             } else {
                 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
             }