| Message ID | 20230621142302.1648383-9-kbastian@mail.uni-paderborn.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | TriCore Privilege Levels | expand |
On 6/21/23 16:23, Bastian Koppelmann wrote: > from ISA v1.6.1 onwards the bit position of ICR.IE changed. > ctx->icr_ie_offset contains the correct value for the ISA version used > by the vCPU. We also need to exit this tb here, as we might have enabled > interrupts. > > Signed-off-by: Bastian Koppelmann<kbastian@mail.uni-paderborn.de> > --- > v3 -> v4: > - Exit tb for RESTORE > > target/tricore/translate.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 71b6209af4..7feab20a7e 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -7956,7 +7956,9 @@ static void decode_sys_interrupts(DisasContext *ctx) case OPC2_32_SYS_RESTORE: if (has_feature(ctx, TRICORE_FEATURE_16)) { if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { - tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); + tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], + ctx->icr_ie_offset, 1); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; } else { generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); }
from ISA v1.6.1 onwards the bit position of ICR.IE changed. ctx->icr_ie_offset contains the correct value for the ISA version used by the vCPU. We also need to exit this tb here, as we might have enabled interrupts. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> --- v3 -> v4: - Exit tb for RESTORE target/tricore/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)