| Message ID | 20230622161646.32005-14-max.chou@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add RISC-V vector cryptographic instruction set support | expand |
On 6/22/23 13:16, Max Chou wrote: > From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> > > This commit adds support for the Zvkg vector-crypto extension, which > consists of the following instructions: > > * vgmul.vv > * vghsh.vv > > Translation functions are defined in > `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in > `target/riscv/vcrypto_helper.c`. > > Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> > [max.chou@sifive.com: Replaced vstart checking by TCG op] > Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> > Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> > Signed-off-by: Max Chou <max.chou@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 5 +- > target/riscv/cpu_cfg.h | 1 + > target/riscv/helper.h | 3 + > target/riscv/insn32.decode | 4 ++ > target/riscv/insn_trans/trans_rvvk.c.inc | 30 ++++++++++ > target/riscv/vcrypto_helper.c | 72 ++++++++++++++++++++++++ > 6 files changed, 113 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index c9a9ff80cd..8e60a122d4 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -118,6 +118,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), > ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), > ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), > + ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), > ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), > ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), > ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), > @@ -1198,8 +1199,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > * In principle Zve*x would also suffice here, were they supported > * in qemu > */ > - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || > - cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { > + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || > + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { > error_setg(errp, > "Vector crypto extensions require V or Zve* extensions"); > return; > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index f859d9e2f5..b125b0b33f 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -85,6 +85,7 @@ struct RISCVCPUConfig { > bool ext_zve64d; > bool ext_zvbb; > bool ext_zvbc; > + bool ext_zvkg; > bool ext_zvkned; > bool ext_zvknha; > bool ext_zvknhb; > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 9220af18e6..a4fe1ff5ca 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -1241,3 +1241,6 @@ DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) > > DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) > DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) > + > +DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32) > +DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 5ca83e8462..b10497afd3 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -957,3 +957,7 @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 > # *** Zvksh vector crypto extension *** > vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 > vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 > + > +# *** Zvkg vector crypto extension *** > +vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 > +vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 > diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc > index af1fb74c38..e5ccb26c45 100644 > --- a/target/riscv/insn_trans/trans_rvvk.c.inc > +++ b/target/riscv/insn_trans/trans_rvvk.c.inc > @@ -510,3 +510,33 @@ static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a) > > GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS) > GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS) > + > +/* > + * Zvkg > + */ > + > +#define ZVKG_EGS 4 > + > +static bool vgmul_check(DisasContext *s, arg_rmr *a) > +{ > + int egw_bytes = ZVKG_EGS << s->sew; > + return s->cfg_ptr->ext_zvkg == true && > + vext_check_isa_ill(s) && > + require_rvv(s) && > + MAXSZ(s) >= egw_bytes && > + vext_check_ss(s, a->rd, a->rs2, a->vm) && > + s->sew == MO_32; > +} > + > +GEN_V_UNMASKED_TRANS(vgmul_vv, vgmul_check, ZVKG_EGS) > + > +static bool vghsh_check(DisasContext *s, arg_rmrr *a) > +{ > + int egw_bytes = ZVKG_EGS << s->sew; > + return s->cfg_ptr->ext_zvkg == true && > + opivv_check(s, a) && > + MAXSZ(s) >= egw_bytes && > + s->sew == MO_32; > +} > + > +GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS) > diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c > index 06c8f4adc7..04e6374211 100644 > --- a/target/riscv/vcrypto_helper.c > +++ b/target/riscv/vcrypto_helper.c > @@ -851,3 +851,75 @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, > vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); > env->vstart = 0; > } > + > +void HELPER(vghsh_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, > + CPURISCVState *env, uint32_t desc) > +{ > + uint64_t *vd = vd_vptr; > + uint64_t *vs1 = vs1_vptr; > + uint64_t *vs2 = vs2_vptr; > + uint32_t vta = vext_vta(desc); > + uint32_t total_elems = vext_get_total_elems(env, desc, 4); > + > + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { > + uint64_t Y[2] = {vd[i * 2 + 0], vd[i * 2 + 1]}; > + uint64_t H[2] = {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; > + uint64_t X[2] = {vs1[i * 2 + 0], vs1[i * 2 + 1]}; > + uint64_t Z[2] = {0, 0}; > + > + uint64_t S[2] = {brev8(Y[0] ^ X[0]), brev8(Y[1] ^ X[1])}; > + > + for (uint j = 0; j < 128; j++) { > + if ((S[j / 64] >> (j % 64)) & 1) { > + Z[0] ^= H[0]; > + Z[1] ^= H[1]; > + } > + bool reduce = ((H[1] >> 63) & 1); > + H[1] = H[1] << 1 | H[0] >> 63; > + H[0] = H[0] << 1; > + if (reduce) { > + H[0] ^= 0x87; > + } > + } > + > + vd[i * 2 + 0] = brev8(Z[0]); > + vd[i * 2 + 1] = brev8(Z[1]); > + } > + /* set tail elements to 1s */ > + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); > + env->vstart = 0; > +} > + > +void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, > + uint32_t desc) > +{ > + uint64_t *vd = vd_vptr; > + uint64_t *vs2 = vs2_vptr; > + uint32_t vta = vext_vta(desc); > + uint32_t total_elems = vext_get_total_elems(env, desc, 4); > + > + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { > + uint64_t Y[2] = {brev8(vd[i * 2 + 0]), brev8(vd[i * 2 + 1])}; > + uint64_t H[2] = {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; > + uint64_t Z[2] = {0, 0}; > + > + for (uint j = 0; j < 128; j++) { > + if ((Y[j / 64] >> (j % 64)) & 1) { > + Z[0] ^= H[0]; > + Z[1] ^= H[1]; > + } > + bool reduce = ((H[1] >> 63) & 1); > + H[1] = H[1] << 1 | H[0] >> 63; > + H[0] = H[0] << 1; > + if (reduce) { > + H[0] ^= 0x87; > + } > + } > + > + vd[i * 2 + 0] = brev8(Z[0]); > + vd[i * 2 + 1] = brev8(Z[1]); > + } > + /* set tail elements to 1s */ > + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); > + env->vstart = 0; > +}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c9a9ff80cd..8e60a122d4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -118,6 +118,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), @@ -1198,8 +1199,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || - cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"); return; diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f859d9e2f5..b125b0b33f 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -85,6 +85,7 @@ struct RISCVCPUConfig { bool ext_zve64d; bool ext_zvbb; bool ext_zvbc; + bool ext_zvkg; bool ext_zvkned; bool ext_zvknha; bool ext_zvknhb; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9220af18e6..a4fe1ff5ca 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1241,3 +1241,6 @@ DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 5ca83e8462..b10497afd3 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -957,3 +957,7 @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 # *** Zvksh vector crypto extension *** vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** Zvkg vector crypto extension *** +vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc index af1fb74c38..e5ccb26c45 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -510,3 +510,33 @@ static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a) GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS) GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS) + +/* + * Zvkg + */ + +#define ZVKG_EGS 4 + +static bool vgmul_check(DisasContext *s, arg_rmr *a) +{ + int egw_bytes = ZVKG_EGS << s->sew; + return s->cfg_ptr->ext_zvkg == true && + vext_check_isa_ill(s) && + require_rvv(s) && + MAXSZ(s) >= egw_bytes && + vext_check_ss(s, a->rd, a->rs2, a->vm) && + s->sew == MO_32; +} + +GEN_V_UNMASKED_TRANS(vgmul_vv, vgmul_check, ZVKG_EGS) + +static bool vghsh_check(DisasContext *s, arg_rmrr *a) +{ + int egw_bytes = ZVKG_EGS << s->sew; + return s->cfg_ptr->ext_zvkg == true && + opivv_check(s, a) && + MAXSZ(s) >= egw_bytes && + s->sew == MO_32; +} + +GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 06c8f4adc7..04e6374211 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -851,3 +851,75 @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); env->vstart = 0; } + +void HELPER(vghsh_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint64_t *vd = vd_vptr; + uint64_t *vs1 = vs1_vptr; + uint64_t *vs2 = vs2_vptr; + uint32_t vta = vext_vta(desc); + uint32_t total_elems = vext_get_total_elems(env, desc, 4); + + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { + uint64_t Y[2] = {vd[i * 2 + 0], vd[i * 2 + 1]}; + uint64_t H[2] = {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; + uint64_t X[2] = {vs1[i * 2 + 0], vs1[i * 2 + 1]}; + uint64_t Z[2] = {0, 0}; + + uint64_t S[2] = {brev8(Y[0] ^ X[0]), brev8(Y[1] ^ X[1])}; + + for (uint j = 0; j < 128; j++) { + if ((S[j / 64] >> (j % 64)) & 1) { + Z[0] ^= H[0]; + Z[1] ^= H[1]; + } + bool reduce = ((H[1] >> 63) & 1); + H[1] = H[1] << 1 | H[0] >> 63; + H[0] = H[0] << 1; + if (reduce) { + H[0] ^= 0x87; + } + } + + vd[i * 2 + 0] = brev8(Z[0]); + vd[i * 2 + 1] = brev8(Z[1]); + } + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); + env->vstart = 0; +} + +void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, + uint32_t desc) +{ + uint64_t *vd = vd_vptr; + uint64_t *vs2 = vs2_vptr; + uint32_t vta = vext_vta(desc); + uint32_t total_elems = vext_get_total_elems(env, desc, 4); + + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { + uint64_t Y[2] = {brev8(vd[i * 2 + 0]), brev8(vd[i * 2 + 1])}; + uint64_t H[2] = {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; + uint64_t Z[2] = {0, 0}; + + for (uint j = 0; j < 128; j++) { + if ((Y[j / 64] >> (j % 64)) & 1) { + Z[0] ^= H[0]; + Z[1] ^= H[1]; + } + bool reduce = ((H[1] >> 63) & 1); + H[1] = H[1] << 1 | H[0] >> 63; + H[0] = H[0] << 1; + if (reduce) { + H[0] ^= 0x87; + } + } + + vd[i * 2 + 0] = brev8(Z[0]); + vd[i * 2 + 1] = brev8(Z[1]); + } + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); + env->vstart = 0; +}