| Message ID | 20230622161646.32005-18-max.chou@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add RISC-V vector cryptographic instruction set support | expand |
On 6/22/23 13:16, Max Chou wrote: > From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> > > Exposes earlier CPU flags allowing the use of the vector cryptography extensions. > > Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> > Signed-off-by: Max Chou <max.chou@sifive.com> > --- > target/riscv/cpu.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index c1956dc29b..48d584ab0d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1714,6 +1714,16 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), > DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), > > + /* Vector cryptography extensions */ > + DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), > + DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), > + DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false), > + DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), > + DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), > + DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), > + DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false), > + DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false), > + We usually add the cpu properties in the same commit that the extension was added, e.g. "x-zvbb" would be added by patch 9. This is no hard rule though. Let's leave this as is and, if a v5 is required for any other reason, you can put each property into its own patch. For now: Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > DEFINE_PROP_END_OF_LIST(), > }; >
On 2023/6/23 1:41 AM, Daniel Henrique Barboza wrote: > > > On 6/22/23 13:16, Max Chou wrote: >> From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> >> >> Exposes earlier CPU flags allowing the use of the vector cryptography >> extensions. >> >> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> >> Signed-off-by: Max Chou <max.chou@sifive.com> >> --- >> target/riscv/cpu.c | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index c1956dc29b..48d584ab0d 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -1714,6 +1714,16 @@ static Property riscv_cpu_extensions[] = { >> DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), >> DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), >> + /* Vector cryptography extensions */ >> + DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), >> + DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), >> + DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false), >> + DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), >> + DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), >> + DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), >> + DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false), >> + DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false), >> + > > We usually add the cpu properties in the same commit that the > extension was > added, e.g. "x-zvbb" would be added by patch 9. This is no hard rule > though. > > Let's leave this as is and, if a v5 is required for any other reason, > you can > put each property into its own patch. For now: > > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > >> DEFINE_PROP_END_OF_LIST(), >> }; Thanks for the suggestion. I'll provide a v5 patch set for the AES related modification. https://lore.kernel.org/qemu-devel/20230620110758.787479-1-richard.henderson@linaro.org/ So I'll also follow the suggestion in v5. With regards, Max
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c1956dc29b..48d584ab0d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1714,6 +1714,16 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), + /* Vector cryptography extensions */ + DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), + DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), + DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false), + DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), + DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), + DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), + DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false), + DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false), + DEFINE_PROP_END_OF_LIST(), };